Inventor
Manohar R. Castelino
Inventor
Santa Clara, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing86%
H04LTransmission of digital information, e.g. telegraphic communication14%
PatentTitleYear
11,017,092Technologies for fast launch of trusted containers202110,963,281Nested virtualization for virtual machine exits202110,956,571Kernel runtime integrity using processor assists202110,901,772Virtualization exceptions202110,552,638Integrity protection of a mandatory access control policy in an operating system using virtual machine extension root operations202010,445,009Systems and methods of controlling memory footprint201910,402,343Event specific page faults for interrupt handling201910,296,366Virtualization exceptions201910,248,786Platform security using processor assists201910,146,570Nested virtualization for virtual machine exits20189,990,494Techniques for enabling co-existence of multiple security measures20189,858,202'Low overhead paged memory runtime protection'20189,852,052Trusted execution of called function20179,824,019'Event specific page faults for interrupt handling'20179,747,123'Technologies for multi-level virtualization'20179,563,455'Virtualization exceptions'20179,454,676'Technologies for preventing hook-skipping attacks using processor virtualization features'20169,449,173'Techniques for enabling co-existence of multiple security measures'20169,436,838'Secure local web application data manager'20169,372,812'Determining policy actions for the handling of data read/write extended page table violations'20169,323,564'Systems, methods and computer program products for bootstrapping a type 1 virtual machine monitor after operating system launch'20169,268,707'Low overhead paged memory runtime protection'20168,719,546'Substitute virtualized-memory page tables'20148,578,080'Secure handling of interrupted events utilizing a virtual interrupt definition table'20138,479,295'Method and apparatus for transparently instrumenting an application program'20137,349,346'Method and apparatus to model routing performance'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2021Patents assigned to INTEL CORP (26)· patent assignee history
2008–2018Based in Sunnyvale, CA, US· patent location history
2013–2021Patents assigned to CASTELINO MANOHAR R (4)· patent assignee history
2013Patents assigned to SAHITA RAVI L (2)· patent assignee history
2013–2021Based in Santa Clara, CA, US· patent location history
2016Patents assigned to CASTELINO MANOHAR RUBEN (1)· patent assignee history
2018Patents assigned to CASTELINO MANOHAR (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 26 | 2008–2021 |
| CASTELINO MANOHAR Rself | 4 | 2013–2021 |
| SAHITA RAVI L | 2 | 2013 |
| CASTELINO MANOHARself | 1 | 2018 |
| CASTELINO MANOHAR RUBENself | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 20 | 2013–2021 |
| Sunnyvale, California, US | 6 | 2008–2018 |