Inventor
Lawrence A. Clevenger
Inventor
Saratoga Springs, NY, US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10DInorganic electric semiconductor devices7%
H10NElectric solid-state devices not otherwise provided for4%
G06FElectric digital data processing4%
H10BElectronic memory devices4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
G09BEducational or demonstration appliances2%
G11CStatic stores2%
PatentTitleYear
11,049,744Optimizing semiconductor binning by feed-forward process adjustment202111,049,727Interleaved structure for molecular manipulation202111,043,494Structure and method for equal substrate to channel height between N and P fin-FETs202111,024,551Metal replacement vertical interconnections for buried capacitance202111,018,007Self aligned pattern formation post spacer etchback in tight pitch configurations202111,018,090Selective CVD alignment-mark topography assist for non-volatile memory202111,004,790Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler material202111,004,736Integrated circuit having a single damascene wiring network202110,998,193Spacer-assisted lithographic double patterning202110,991,619Top via process accounting for misalignment by increasing reliability202110,985,063Semiconductor device with local connection202110,978,393Hybrid dielectric scheme for varying liner thickness and manganese concentration202110,978,343Interconnect structure having fully aligned vias202110,971,030Remote physical training202110,964,588Selective ILD deposition for fully aligned via with airgap202110,957,582Self aligned via and pillar cut for at least a self aligned double pitch202110,957,583Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs202110,957,646Hybrid BEOL metallization utilizing selective reflection mask202110,957,581Self aligned via and pillar cut for at least a self aligned double pitch202110,950,662Resistive memory device with meshed electrodes202110,950,787Method having resistive memory crossbar array employing selective barrier layer growth202110,950,722Vertical gate all-around transistor202110,943,972Precision BEOL resistors202110,943,866Method and structure to construct cylindrical interconnects to reduce resistance202110,937,653Multiple patterning scheme integration with planarized cut patterning202110,936,782Semiconductor process modeling to enable skip via in place and route flow202110,930,553Forming self-aligned vias and air-gaps in semiconductor fabrication202110,923,575Low resistance contact for transistors202110,915,620Paint on micro chip touch screens202110,912,986Dynamic rigidity mechanism202110,916,501Back end of line electrical fuse structure and method of fabrication202110,916,154Language learning and speech enhancement through natural language processing202110,916,699Resistive memory crossbar array employing selective barrier layer growth202110,901,317Extreme ultraviolet (EUV) lithography patterning methods utilizing EUV resist hardening20217,394,332'Micro-cavity MEMS device and method of fabricating same'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2021Patents assigned to IBM (32)· patent assignee history
2008–2021Based in Lagrangeville, NY, US· patent location history
2021Patents assigned to TESSERA INC (3)· patent assignee history
2021Patents assigned to INT BUSINESSS MACHINES CORPORATION (1)· patent assignee history
2021Patents assigned to ST MICROELECTRONICS INC (1)· patent assignee history
2021Based in Saratoga Springs, NY, US· patent location history
2021Based in Rhinebeck, NY, US· patent location history
2021Based in Dutchess County, NY, US· patent location history
2021Based in Hopewell Junction, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 32 | 2008–2021 |
| TESSERA INC | 3 | 2021 |
| INT BUSINESSS MACHINES CORPORATION | 1 | 2021 |
| ST MICROELECTRONICS INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga Springs, New York, US | 19 | 2021 |
| Rhinebeck, New York, US | 9 | 2021 |
| Lagrangeville, New York, US | 5 | 2008–2021 |
| Dutchess County, New York, US | 1 | 2021 |
| Hopewell Junction, New York, US | 1 | 2021 |