Inventor

Randy W. Mann

Inventor

Jericho, VT, US

Overview

1995–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 109 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices29%

H10BElectronic memory devices18%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

G11CStatic stores8%

H01LSemiconductor devices8%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%

G06FElectric digital data processing2%

C23CCoating metallic material1%

C30BSingle-crystal growth1%

PatentTitleYear

11,037,937SRAM bit cells formed with dummy structures2021 10,818,674Structures and SRAM bit cells integrating complementary field-effect transistors2020 10,629,602Static random access memory cells with arranged vertical-transport field-effect transistors2020 10,497,692SRAM structure with alternate gate pitches2019 10,439,064Dual port vertical transistor memory cell2019 10,403,629Six-transistor (6T) SRAM cell structure2019 10,332,897Method of reducing fin width in FinFet SRAM array to mitigate low voltage strap bit fails2019 10,163,914Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails2018 10,109,637Cross couple structure for vertical transistors2018 10,068,902Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method2018 10,068,660Methods, apparatus, and system for global healing of write-limited die through bias temperature instability2018 9,916,212'Method, apparatus, and system for targeted healing of write fails through bias temperature instability'2018 9,761,594'Hardmask for a halo/extension implant of a static random access memory (SRAM) layout'2017 9,704,600'Method, apparatus, and system for global healing of write-limited die through bias temperature instability'2017 9,601,187'Method, apparatus, and system for global healing of stability-limited die through bias temperature instability'2017 9,601,188'Method, apparatus and system for targeted healing of stability failures through bias temperature instability'2017 9,564,375'Structures and methods for extraction of device channel width'2017 9,530,488'Methods, apparatus and system determining dual port DC contention margin'2016 9,484,300'Device resulting from printing minimum width semiconductor features at non-minimum pitch'2016 9,372,226'Wafer test structures and methods of providing wafer test structures'2016 9,337,204'Memory cell'2016 9,263,349'Printing minimum width semiconductor features at non-minimum pitch and resulting device'2016 9,219,040'Integrated circuit with semiconductor fin fuse'2015 9,202,552'Dual port SRAM bitcell structures with improved transistor arrangement'2015 9,069,922'Modeling memory cell skew sensitivity'2015 9,048,136'SRAM cell with individual electrical device threshold control'2015 9,029,956'SRAM cell with individual electrical device threshold control'2015 8,947,912'Memory cell including unidirectional gate conductors and contacts'2015 8,907,687'Integrated circuit with stress generator for stressing test devices'2014 8,597,994'Semiconductor device and method of fabrication'2013 8,569,116'Integrated circuit with a fin-based fuse, and related fabrication method'2013 8,563,398'Electrically conductive path forming below barrier oxide layer and integrated circuit'2013 8,099,688'Circuit design'2012 7,989,922'Highly tunable metal-on-semiconductor trench varactor'2011 7,923,840'Electrically conductive path forming below barrier oxide layer and integrated circuit'2011 7,745,863'Flip FERAM cell and method to form same'2010 7,696,034'Methods of base formation in a BiCOMS process'2010 7,679,083'Semiconductor integrated test structures for electron beam inspection of semiconductor wafers'2010 7,466,604'SRAM voltage control for improved operational margins'2008 7,402,857'Flip FERAM cell and method to form same'2008 7,390,721'Methods of base formation in a BiCMOS process'2008 7,313,032'SRAM voltage control for improved operational margins'2007 7,217,969'Flip FERAM cell and method to form same'2007 7,193,262'Low-cost deep trench decoupling capacitor device and process of manufacture'2007 7,190,007'Isolated fully depleted silicon-on-insulator regions by selective etch'2007 7,186,573'Flip FERAM cell and method to form same'2007 7,166,904'Structure and method for local resistor element in integrated circuit technology'2007 7,087,486'Method for scalable, low-cost polysilicon capacitor in a planar DRAM'2006 7,087,477'FinFET SRAM cell using low mobility plane for cell stability and method for forming'2006 7,075,153'Grounded body SOI SRAM cell'2006 7,057,180'Detector for alpha particle or cosmic ray'2006 7,005,334'Zero threshold voltage pFET and method of making same'2006 6,967,351'Finfet SRAM cell using low mobility plane for cell stability and method for forming'2005 6,965,133'Method of base formation in a BiCMOS process'2005 6,962,838'High mobility transistors in SOI and method for forming'2005 6,946,376'Symmetric device with contacts self aligned to gate'2005 6,917,221'Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits'2005 6,900,505'Method of forming refractory metal contact in an opening, and resulting structure'2005 6,891,419'Methods and apparatus for employing feedback body control in cross-coupled inverters'2005 6,881,672'Selective silicide blocking'2005 6,825,530'Zero Threshold Voltage pFET and method of making same'2004 6,815,751'Structure for scalable, low-cost polysilicon DRAM in a planar capacitor'2004 6,778,449'Method and design for measuring SRAM array leakage macro (ALM)'2004 6,774,017'Method and structures for dual depth oxygen layers in silicon-on-insulator processes'2004 6,762,121'Method of forming refractory metal contact in an opening, and resulting structure'2004 6,700,163'Selective silicide blocking'2004 6,646,305'Grounded body SOI SRAM cell'2003 6,624,478'High mobility transistors in SOI and method for forming'2003 6,624,475'SOI low capacitance body contact'2003 6,614,124'Simple 4T static ram cell for low power CMOS applications'2003 6,555,859'Flip FERAM cell and method to form same'2003 6,515,317'Sidewall charge-coupled device with multiple trenches in multiple wells'2003 6,512,296'Semiconductor structure having heterogenous silicide regions having titanium and molybdenum'2003 6,498,096'Borderless contact to diffusion with respect to gate conductor and methods for fabricating'2002 6,489,223'Angled implant process'2002 6,476,445'Method and structures for dual depth oxygen layers in silicon-on-insulator processes'2002 6,445,050'Symmetric device with contacts self aligned to gate'2002 6,441,410'MOSFET with lateral resistor ballasting'2002 6,420,746'Three device DRAM cell with integrated capacitor and local interconnect'2002 6,395,624'Method for forming implants in semiconductor fabrication'2002 6,387,596'Method of forming resist images by periodic pattern removal'2002 6,380,063'Raised wall isolation device with spacer isolated contacts and the method of so forming'2002 6,368,903'SOI low capacitance body contact'2002 6,338,921'Mask with linewidth compensation and method of making same'2002 6,335,272'Buried butted contact and method for fabricating'2002 6,333,202'Flip FERAM cell and method to form same'2001 6,300,228'Multiple precipitation doping process'2001 6,294,419'Structure and method for improved latch-up using dual depth STI with impurity implant'2001 6,268,286'Method of fabricating MOSFET with lateral resistor with ballasting'2001 6,215,190'Borderless contact to diffusion with respect to gate conductor and methods for fabricating'2001 6,187,617'Semiconductor structure having heterogeneous silicide regions and method for forming same'2001 6,187,679'Low temperature formation of low resistivity titanium silicide'2001 6,153,934'Buried butted contact and method for fabricating'2000 6,144,086'Structure for improved latch-up using dual depth STI with impurity implant'2000 6,140,171'FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication'2000 6,022,766'Semiconductor structure incorporating thin film transistors, and methods for its manufacture'2000 6,008,112'Method for planarized self-aligned floating gate to isolation'1999 5,899,713'Method of making NVRAM cell with planar control gate'1999 5,828,131'Low temperature formation of low resistivity titanium silicide'1998 5,757,050'Field effect transistor having contact layer of transistor gate electrode material'1998 5,744,384'Semiconductor structures which incorporate thin film transistors'1998 5,677,563'Gate stack structure of a field effect transistor'1997 5,675,185'Semiconductor structure incorporating thin film transistors with undoped cap oxide layers'1997 5,672,901'Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits'1997 5,670,812'Field effect transistor having contact layer of transistor gate electrode material'1997 5,510,295'Method for lowering the phase transformation temperature of a metal silicide'1996 5,496,771'Method of making overpass mask/insulator for local interconnects'1996 5,485,095'Fabrication test circuit and method for signalling out-of-spec resistance in integrated circuit structure'1996 5,453,400'Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2013Patents assigned to IBM (78)· patent assignee history

1995–2010Based in Jericho, VT, US· patent location history

2004–2013Based in Poughquag, NY, US· patent location history

2007Based in Williston, VT, US· patent location history

2011–2012Based in Burlington, NC, US· patent location history

2012–2015Patents assigned to MANN RANDY W (9)· patent assignee history

2013–2020Patents assigned to GLOBALFOUNDRIES INC (27)· patent assignee history

2013–2021Based in Milton, NY, US· patent location history

2015–2017Patents assigned to GLOBAL FOUNDRIES INC (2)· patent assignee history

2015Patents assigned to LUNING SCOTT D (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	78	1995–2013
GLOBALFOUNDRIES INC	27	2013–2020
MANN RANDY Wself	9	2012–2015
GLOBAL FOUNDRIES INC	2	2015–2017
LUNING SCOTT D	2	2015

Locations

Location	Patents	Span
Jericho, VT, US	59	1995–2010
Milton, New York, US	31	2013–2021
Poughquag, New York, US	15	2004–2013
Burlington, NC, US	2	2011–2012
Williston, VT, US	1	2007