Inventor

John F. Schreck

Inventor

Lucas, TX, US

Overview

1988–2021

Patent span

Physics

Primary field (CPC G)

Patents· 82 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores57%

G06FElectric digital data processing11%

H03KPulse technique6%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%

G01RMeasuring electric variables3%

H03MCoding3%

G05FSystems for regulating electric or magnetic variables2%

H01LSemiconductor devices2%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%

H10DInorganic electric semiconductor devices2%

PatentTitleYear

11,037,621Sensing techniques using a charge transfer device2021 10,930,326Sensing architecture2021 10,930,337Write techniques for a memory device with a charge transfer device2021 10,923,180Sensing techniques using a charge transfer device2021 10,832,769Memory device with a charge transfer device2020 10,832,768Data storage based on data polarity2020 10,818,343Techniques for charging a sense component2020 10,699,783Sensing techniques using a moving reference2020 10,665,292Sensing techniques using charge transfer device2020 10,650,888Tuning voltages in a read circuit2020 10,468,382Signal delivery in stacked device2019 10,153,007Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods2018 9,324,690'Signal delivery in stacked device'2016 9,246,382'Charge pump including supply voltage-based control signal level'2016 9,224,436'Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods'2015 9,183,952'Apparatuses and methods for compressing data received over multiple memory accesses'2015 8,963,604'Methods, apparatuses, and circuits for bimodal disable circuits'2015 8,880,974'Memory system and method using ECC with flag bit to identify modified data'2014 8,692,603'Methods, apparatuses, and circuits for bimodal disable circuits'2014 8,601,341'Memory system and method using ECC with flag bit to identify modified data'2013 8,519,767'Methods, apparatuses, and circuits for bimodal disable circuits'2013 8,413,007'Memory system and method using ECC with flag bit to identify modified data'2013 8,397,129'Memory array error correction apparatus, systems, and methods'2013 8,181,086'Memory array error correction apparatus, systems, and methods'2012 8,106,520'Signal delivery in stacked device'2012 7,945,840'Memory array error correction apparatus, systems, and methods'2011 7,900,120'Memory system and method using ECC with flag bit to identify modified data'2011 7,400,124'Apparatus and methods for regulated voltage'2008 7,200,052'Apparatus and methods for regulated voltage'2007 7,184,352'Memory system and method using ECC to achieve low power refresh'2007 7,126,317'Apparatus and methods for regulated voltage'2006 7,106,637'Asynchronous interface circuit and method for a pseudo-static memory device'2006 7,072,230'Method and apparatus for standby power reduction in semiconductor devices'2006 6,965,537'Memory system and method using ECC to achieve low power refresh'2005 6,961,272'Physically alternating sense amplifier activation'2005 6,873,562'Method and apparatus for standby power reduction in semiconductor devices'2005 6,862,229'Physically alternating sense amplifier activation'2005 6,853,591'Circuit and method for decreasing the required refresh rate of DRAM devices'2005 6,838,337'Sense amplifier and architecture for open digit arrays'2005 6,819,621'Method and apparatus for standby power reduction in semiconductor devices'2004 6,721,221'Sense amplifier and architecture for open digit arrays'2004 6,707,729'Physically alternating sense amplifier activation'2004 6,690,606'Asynchronous interface circuit and method for a pseudo-static memory device'2004 6,614,711'Row decoder scheme for flash memory devices'2003 6,556,503'Methods and apparatus for reducing decoder area'2003 6,512,705'Method and apparatus for standby power reduction in semiconductor devices'2003 6,049,483'Nonvolatile memory device having program and/or erase voltage clamp'2000 5,835,395'Eprom pinout option'1998 5,636,226'Fault sensing circuit and method'1997 5,513,064'Method and device for improving I/O ESD tolerance'1996 5,491,658'Column decoder for virtual ground memory array'1996 5,412,603'Method and circuitry for programming floating-gate memory cell using a single low-voltage supply'1995 5,365,486'Method and circuitry for refreshing a flash electrically erasable, programmable read only memory'1994 5,313,427'EEPROM array with narrow margin of voltage thresholds after erase'1994 5,313,432'Segmented, multiple-decoder memory array and method for programming a memory array'1994 5,311,480'Method and apparatus for EEPROM negative voltage wordline decoding'1994 5,287,536'Nonvolatile memory array wordline driver circuit with voltage translator circuit'1994 5,287,310'Memory with I/O mappable redundant columns'1994 5,287,315'Skewed reference to improve ones and zeros in EPROM arrays'1994 5,278,458'Threshold/voltage detection circuit'1994 5,197,029'Common-line connection for integrated memory array'1993 5,182,726'Circuit and method for discharging a memory array'1993 5,170,077'Voltage level detecting circuit'1992 5,157,280'Switch for selectively coupling a power supply to a power bus'1992 5,151,880'Method and apparatus for determining the field position of an integrated circuit within a reticle area'1992 5,140,554'Integrated circuit fuse-link tester and test method'1992 5,132,933'Bias circuitry for nonvolatile memory array'1992 5,124,945'Method and apparatus for verifying the state of a plurality of electrically programmable memory cells'1992 5,120,999'Output-buffer noise-control circuit'1992 5,023,837'Bitline segmentation in logic arrays'1991 5,022,008'PROM speed measuring method'1991 5,020,026'Method and apparatus for reading and programming electrically programmable memory cells'1991 4,868,790'Reference circuit for integrated memory arrays having virtual ground connections'1989 4,858,187'Programming implementation circuit'1989 4,820,941'Decoder driver circuit for programming high-capacitance lines'1989 4,802,121'Memory array with partitioned bit lines'1989 4,797,857'Array discharge for biased array'1989 4,760,554'Staggered contacts in arrays of programmable memory cells'1988 4,750,024'Offset floating gate EPROM memory cell'1988 4,740,925'Extra row for testing programmability and speed of ROMS'1988 4,723,225'Programming current controller'1988 4,722,075'Equalized biased array for PROMS and EPROMS'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2000Patents assigned to TEXAS INSTRUMENTS INC (35)· patent assignee history

1988–1998Based in Houston, TX, US· patent location history

1992–2016Patents assigned to SCHRECK JOHN F (6)· patent assignee history

1995–2021Based in Lucas, TX, US· patent location history

2003–2021Patents assigned to MICRON TECHNOLOGY INC (46)· patent assignee history

2012–2016Patents assigned to ADVANI RAHUL (2)· patent assignee history

2012–2013Patents assigned to DAUENBAUGH TODD A (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	46	2003–2021
TEXAS INSTRUMENTS INC	35	1988–2000
SCHRECK JOHN Fself	6	1992–2016
ADVANI RAHUL	2	2012–2016
DAUENBAUGH TODD A	2	2012–2013

Locations

Location	Patents	Span
Lucas, Texas, US	48	1995–2021
Houston, Texas, US	34	1988–1998