Inventor
Ravi H. Motwani
Inventor
San Diego, CA, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing36%
H03MCoding31%
G11CStatic stores24%
H04LTransmission of digital information, e.g. telegraphic communication4%
G11BInformation storage based on relative movement between record carrier and transducer3%
G05BControl or regulating systems in general1%
H04BTransmission1%
PatentTitleYear
11,086,714Permutation of bit locations to reduce recurrence of bit error patterns in a memory device202110,944,428Device, system and method for determining bit reliability information202110,942,799Defective bit line management in connection with a memory access202110,908,996Distribution of a codeword across individual storage units to reduce the bit error rate202110,879,938Erasure coding to mitigate media defects for distributed die ECC202010,839,916One-sided soft reads202010,707,901Die-wise residual bit error rate (RBER) estimation for memories202010,621,035Techniques for correcting data errors in memory devices202010,599,515Transfer of encoded data stored in non-volatile memory for decoding by a controller of a memory device202010,579,473Mitigating silent data corruption in error control coding202010,547,327Self-configuring error control coding202010,481,974Apparatus, non-volatile memory storage device and method for detecting drift in non-volatile memory201910,454,495Apparatus and method for mapping binary to ternary and its reverse201910,176,042Using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units201910,073,731Error correction in memory201810,033,411Adjustable error protection for stored data201810,009,043Technologies for providing efficient error correction with half product codes20189,946,598Handling open circuits while writing data by moving them to the least vulnerable location in an error correction code codeword20189,911,509'Counter to locate faulty die in a distributed codeword storage system'20189,912,355'Distributed concatenated error correction'20189,842,022'Technologies for reducing latency in read operations'20179,819,362'Apparatus and method for detecting and mitigating bit-line opens in flash memory'20179,798,622'Apparatus and method for increasing resilience to raw bit error rate'20179,729,171'Techniques for soft decision decoding of encoded data'20179,698,830'Single-bit first error correction'20179,652,321'Recovery algorithm in non-volatile memory'20179,619,324'Error correction in non—volatile memory'20179,588,841'Using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units'20179,535,777'Defect management policies for NAND flash memory'20179,502,104'Multi-level cell (MLC) non-volatile memory data reading method and apparatus'20169,438,287'Apparatus and method for mitigating loss of signal content'20169,323,609'Data storage and variable length error correction information'20169,317,364'Memory controller with distribution transformer'20169,298,552'Using read values from previous decoding operations to calculate soft bit information in an error recovery operation'20169,294,224'Maximum-likelihood decoder in a memory controller for synchronization'20169,250,990'Use of error correction pointers to handle errors in memory'20169,093,170'Multi-level cell (MLC) non-volatile memory data reading method and apparatus'20159,043,681'Reconstructing codewords using a side channel'20159,037,943'Identification of non-volatile memory die for use in remedial action'20158,959,407'Scaling factors for hard decision reads of codewords distributed across die'20158,943,385'NAND memory management'20158,804,421'Center read reference voltage determination based on estimated probability density function'20148,667,360'Apparatus, system, and method for generating and decoding a longer linear block codeword using a shorter block length'20148,549,380'Non-volatile memory error mitigation'20138,549,382'Storage drive with LDPC coding'20138,473,828'Minimal hardware implementation of non-parity and parity trellis'20138,091,009'Symbol by symbol map detection for signals corrupted by colored and/or signal dependent noise'20127,733,590'Optimal synchronization mark/address mark construction'20107,689,896'Minimal hardware implementation of non-parity and parity trellis'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2013Patents assigned to BROADCOM CORP (4)· patent assignee history
2010–2013Based in Longmont, CO, US· patent location history
2012–2016Patents assigned to MOTWANI RAVI (3)· patent assignee history
2013–2021Patents assigned to INTEL CORP (45)· patent assignee history
2013–2016Patents assigned to MOTWANI RAVI H (5)· patent assignee history
2013–2020Based in San Diego, CA, US· patent location history
2013–2014Based in Santa Clara, CA, US· patent location history
2015Patents assigned to KALAVADE PRANAV (1)· patent assignee history
2018–2021Based in Fremont, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 45 | 2013–2021 |
| MOTWANI RAVI Hself | 5 | 2013–2016 |
| BROADCOM CORP | 4 | 2010–2013 |
| MOTWANI RAVIself | 3 | 2012–2016 |
| KALAVADE PRANAV | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Diego, California, US | 32 | 2013–2020 |
| Fremont, California, US | 11 | 2018–2021 |
| Longmont, CO, US | 4 | 2010–2013 |
| Santa Clara, California, US | 2 | 2013–2014 |