Inventor
Jairus Legaspi Pisigan
Inventor
Singapore, SG
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1081%
H01LSemiconductor devices13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
PatentTitleYear
9,721,925'Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure'20179,472,427'Semiconductor device and method of forming leadframe with notched fingers for stacking semiconductor die'20169,034,692'Integrated circuit packaging system with a flip chip and method of manufacture thereof'20158,941,219'Etched recess package on package system'20158,890,328'Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers'20148,872,320'Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure'20148,802,555'Integrated circuit packaging system with interconnects and method of manufacture thereof'20148,802,505'Semiconductor device and method of forming a protective layer on a backside of the wafer'20148,766,428'Integrated circuit packaging system with flip chip and method of manufacture thereof'20148,652,881'Integrated circuit package system with anti-peel contact pads'20148,643,157'Integrated circuit package system having perimeter paddle'20148,637,394'Integrated circuit package system with flex bump'20148,558,369'Integrated circuit packaging system with interconnects and method of manufacture thereof'20138,513,801'Integrated circuit package system'20138,502,371'Integrated circuit package system with extended corner leads'20138,354,742'Method and apparatus for a package having multiple stacked die'20138,338,233'Method of manufacture of integrated circuit packaging system with stacked integrated circuit'20128,304,869'Fan-in interposer on lead frame for an integrated circuit package on package system'20128,304,337'Integrated circuit packaging system with bond wire pads and method of manufacture thereof'20128,278,148'Integrated circuit package system with leads separated from a die paddle'20128,258,614'Integrated circuit package system with package integration'20128,236,607'Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof'20128,148,825'Integrated circuit package system with leadfinger'20128,148,208'Integrated circuit package system with leaded package and method for manufacturing thereof'20128,129,827'Integrated circuit package system with package encapsulation having recess'20128,110,440'Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure'20128,105,915'Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers'20128,106,499'Integrated circuit packaging system with a dual substrate package and method of manufacture thereof'20128,106,502'Integrated circuit packaging system with plated pad and method of manufacture thereof'20128,080,867'Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof'20118,067,825'Integrated circuit package system with multiple die'20117,977,780'Multi-layer package-on-package system'20117,977,782'Integrated circuit package system with dual connectivity'20117,932,130'Method for forming an etched recess package on package system'20117,915,724'Integrated circuit packaging system with base structure device'20117,915,716'Integrated circuit package system with leadframe array'20117,777,354'Integrated circuit package system with leaded package'20107,691,674'Integrated circuit packaging system with stacked device and method of manufacturing thereof'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2017Patents assigned to STATS CHIPPAC LTD (37)· patent assignee history
2010–2017Based in Singapore, SG· patent location history
2011–2015Patents assigned to PISIGAN JAIRUS LEGASPI (24)· patent assignee history
2011–2015Patents assigned to CAMACHO ZIGMUND RAMIREZ (22)· patent assignee history
2011–2015Patents assigned to BATHAN HENRY DESCALZO (17)· patent assignee history
2012–2015Patents assigned to TAY LIONEL CHIEN HUI (11)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| STATS CHIPPAC LTD | 37 | 2010–2017 |
| PISIGAN JAIRUS LEGASPIself | 24 | 2011–2015 |
| CAMACHO ZIGMUND RAMIREZ | 22 | 2011–2015 |
| BATHAN HENRY DESCALZO | 17 | 2011–2015 |
| TAY LIONEL CHIEN HUI | 11 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Singapore, SG | 38 | 2010–2017 |