Inventor

Bret K. Street

Inventor

Meridian, ID, US

Overview

2001–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 67 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%

Y10TTechnical subjects covered by former us classification15%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

G01RMeasuring electric variables10%

H01LSemiconductor devices10%

B33YAdditive manufacturing, i.e. manufacturing of three-dimensional [3d] objects by additive deposition, additive agglomeration or additive layering, e.g. by 3d printing, stereolithography or selective laser sintering9%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation8%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%

B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form1%

F03GSpring, weight, inertia or like motors1%

PatentTitleYear

11,114,415Semiconductor device with a layered protection mechanism and associated systems, devices, and methods2021 10,861,797Electrically or temperature activated shape-memory materials for warpage control2020 10,840,209Methods and systems for manufacturing semiconductor devices2020 10,840,210Methods and systems for manufacturing semiconductor devices2020 10,748,857Die features for self-alignment during die bonding2020 10,741,528Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods2020 10,615,150Semiconductor device with a layered protection mechanism and associated systems, devices, and methods2020 10,580,720Silicon interposer with fuse-selectable routing array2020 10,580,710Semiconductor device with a protection mechanism and associated systems, devices, and methods2020 10,475,771Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods2019 10,381,329Semiconductor device with a layered protection mechanism and associated systems, devices, and methods2019 10,103,134Methods of manufacturing multi-die semiconductor device packages and related assemblies2018 10,043,688Method for mount tape die release system for thin die ejection2018 9,865,578'Methods of manufacturing multi-die semiconductor device packages and related assemblies'2018 9,786,612'Methods of processing wafer-level assemblies to reduce warpage, and related assemblies'2017 9,589,933'Methods of processing wafer-level assemblies to reduce warpage, and related assemblies'2017 7,858,420'Microelectronic imaging units and methods of manufacturing microelectronic imaging units'2010 7,786,574'Microelectronic imaging units'2010 7,691,660'Methods of manufacturing microelectronic imaging units on a microfeature workpiece'2010 7,655,507'Microelectronic imaging units and methods of manufacturing microelectronic imaging units'2010 7,557,452'Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same'2009 7,511,374'Microelectronic imaging units having covered image sensors'2009 7,498,606'Microelectronic imaging units and methods of manufacturing microelectronic imaging units'2009 7,491,570'Die package having an adhesive flow restriction area'2009 7,476,955'Die package having an adhesive flow restriction area'2009 7,439,598'Microelectronic imaging units'2008 7,416,913'Methods of manufacturing microelectronic imaging units with discrete standoffs'2008 7,417,294'Microelectronic imaging units and methods of manufacturing microelectronic imaging units'2008 7,402,453'Microelectronic imaging units and methods of manufacturing microelectronic imaging units'2008 7,364,934'Microelectronic imaging units and methods of manufacturing microelectronic imaging units'2008 7,276,393'Microelectronic imaging units and methods of manufacturing microelectronic imaging units'2007 7,238,543'Methods for marking a bare semiconductor die including applying a tape having energy-markable properties'2007 7,239,015'Heat sinks including nonlinear passageways'2007 7,205,654'Programmed material consolidation methods for fabricating heat sinks'2007 7,105,366'Method for in-line testing of flip-chip semiconductor assemblies'2006 7,094,618'Methods for marking a packaged semiconductor die including applying tape and subsequently marking the tape'2006 7,074,648'Method for packaging flip-chip semiconductor assemblies'2006 7,026,191'Stereolithographic method for fabricating heat sinks, stereolithographically fabricated heat sinks, and semiconductor devices including same'2006 7,005,878'Method for in-line testing of flip-chip semiconductor assemblies'2006 6,982,177'Method for in-line testing of flip-chip semiconductor assemblies'2006 6,972,200'Method for manufacturing flip-chip semiconductor assembly'2005 6,967,113'Method for in-line testing of flip-chip semiconductor assemblies'2005 6,962,826'Method for in-line testing of flip-chip semiconductor assemblies'2005 6,953,699'Method for in-line testing of flip-chip semiconductor assemblies'2005 6,953,700'Method for in-line testing of flip-chip semiconductor assemblies'2005 6,954,081'Method for in-line testing of flip-chip semiconductor assemblies'2005 6,949,943'Method for in-line testing of flip-chip semiconductor assemblies'2005 6,916,683'Methods of fabricating a molded ball grid array'2005 6,891,108'Semiconductor packages and methods for making the same'2005 6,858,927'Semiconductor packages and methods for making the same'2005 6,833,510'Semiconductor packages and methods for making the same'2004 6,791,198'Method and apparatus for gate blocking X-outs during a molding process'2004 6,779,258'Semiconductor packages and methods for making the same'2004 6,776,599'Method and apparatus for gate blocking X-outs during a molding process'2004 6,750,070'Process for manufacturing flip-chip semiconductor assembly'2004 6,734,032'Method and apparatus for marking a bare semiconductor die'2004 6,730,998'Stereolithographic method for fabricating heat sinks, stereolithographically fabricated heat sinks, and semiconductor devices including same'2004 6,692,978'Methods for marking a bare semiconductor die'2004 6,548,764'Semiconductor packages and methods for making the same'2003 6,545,498'Method for in-line testing of flip-chip semiconductor assemblies'2003 6,523,254'Method for gate blocking x-outs during a molding process'2003 6,524,881'Method and apparatus for marking a bare semiconductor die'2003 6,503,781'Molded ball grid array'2003 6,472,901'Method for in-line testing of flip-chip semiconductor assemblies'2002 6,400,574'Molded ball grid array'2002 6,369,602'Method for in-line testing of flip-chip semiconductor assemblies'2002 6,329,832'Method for in-line testing of flip-chip semiconductor assemblies'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to MICRON TECHNOLOGY INC (64)· patent assignee history

2001–2021Based in Meridian, ID, US· patent location history

2009–2010Patents assigned to APTINA IMAGING CORP (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	64	2001–2021
APTINA IMAGING CORP	3	2009–2010

Locations

Location	Patents	Span
Meridian, ID, US	67	2001–2021