Inventor
Kurt A. Feiste
Inventor
Austin, TX, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing95%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
PatentTitleYear
10,970,079Parallel dispatching of multi-operation instructions in a multi-slice computer processor202110,936,321Instruction chaining202110,877,763Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor202010,838,728Parallel slice processor shadowing states of hardware threads across execution slices202010,740,107Operation of a multi-slice processor implementing load-hit-store handling202010,671,399Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core202010,671,398Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core202010,496,412Parallel dispatching of multi-operation instructions in a multi-slice computer processor201910,437,756Operation of a multi-slice processor implementing datapath steering201910,417,152Operation of a multi-slice processor implementing datapath steering201910,120,683Supporting even instruction tag ('ITAG') requirements in a multi-slice processor using null internal operations (IOPs)201810,102,001Parallel slice processor shadowing states of hardware threads across execution slices20189,977,677Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port20189,971,687Operation of a multi-slice processor with history buffers storing transaction memory state information20188,200,946'Issue unit for placing a processor into a gradual slow mode of operation'20128,082,423'Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates'20118,041,928'Information handling system with real and virtual load/store instruction issue queue'20117,953,960'Method and apparatus for delaying a load miss flush until issuing the dependent instruction'20117,949,857'Method and system for determining multiple unused registers in a processor'20117,818,544'Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition'20107,437,539'Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline'20087,434,033'Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline'20087,412,589'Method to detect a stalled instruction stream and serialize micro-operation execution'20087,370,176'System and method for high frequency stall design'20087,350,056'Method and apparatus for issuing instructions from an issue queue in an information handling system'20086,658,534'Mechanism to reduce instruction cache miss penalties and methods therefor'20036,349,382'System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order'20026,266,767'Apparatus and method for facilitating out-of-order execution of load instructions'20016,167,500'Mechanism for queuing store data and method therefor'20006,134,646'System and method for executing and completing store instructions'20006,070,238'Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction'20006,021,485'Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching'20005,974,259'Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels'19995,963,978'High level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicators'19995,926,830'Data processing system and method for maintaining coherency between high and low level caches using inclusive states'19995,860,100'Pipelined flushing of a high level cache and invalidation of lower level caches'19995,832,276'Resolving processor and system bus address collision in a high-level cache'19985,822,765'System and method for resolving contention arising from execution of cache coherency operations in a multiple cache computer system'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2021Patents assigned to IBM (38)· patent assignee history
1998–2021Based in Austin, TX, US· patent location history
2011Patents assigned to ABERNATHY CHRISTOPHER MICHAEL (1)· patent assignee history
2011Patents assigned to FEISTE KURT ALAN (1)· patent assignee history
2012Patents assigned to ABERNATHY CHRISTOPHER M (1)· patent assignee history
2012Patents assigned to FEISTE KURT A (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 38 | 1998–2021 |
| ABERNATHY CHRISTOPHER M | 1 | 2012 |
| ABERNATHY CHRISTOPHER MICHAEL | 1 | 2011 |
| FEISTE KURT Aself | 1 | 2012 |
| FEISTE KURT ALANself | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 38 | 1998–2021 |