Inventor
Roy R. Yu
Inventor
Poughkeepsie, NY, US
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
H10DInorganic electric semiconductor devices17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10BElectronic memory devices12%
A61BDiagnosis7%
A61NElectrotherapy5%
B82YSpecific uses or applications of nanostructures5%
A61KPreparations for medical, dental or toiletry purposes2%
A61LMethods or apparatus for sterilising materials or objects in general2%
C12QMeasuring or testing processes involving enzymes, nucleic acids or microorganisms2%
PatentTitleYear
10,694,950Probe structure for physiological measurements using surface enhanced Raman spectroscopy202010,694,951Probe structure for physiological measurements using surface enhanced Raman spectroscopy202010,669,153Neuro-chemical sensor with selectively permeable membrane on nano-electrode202010,583,282Neuro-stem cell stimulation and growth enhancement with implantable nanodevice20209,171,742'Alignment of integrated circuit chip stack'20158,962,448'Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier'20158,738,167'3D integrated circuit device fabrication with precisely controllable substrate removal'20148,664,081'Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier'20148,629,553'3D integrated circuit device fabrication with precisely controllable substrate removal'20148,546,188'Bow-balanced 3D chip stacking'20138,492,869'3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer'20138,399,336'Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer'20138,298,914'3D integrated circuit device fabrication using interface wafer as permanent carrier'20128,129,256'3D integrated circuit device fabrication with precisely controllable substrate removal'20126,339,527'Thin film capacitor on ceramic'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2020Patents assigned to IBM (15)· patent assignee history
2002–2020Based in Poughkeepsie, NY, US· patent location history
2012–2015Patents assigned to YU ROY R (9)· patent assignee history
2012–2015Patents assigned to FAROOQ MUKTA G (8)· patent assignee history
2012–2015Patents assigned to HANNON ROBERT (8)· patent assignee history
2012–2015Patents assigned to IYER SUBRAMANIAN S (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 15 | 2002–2020 |
| YU ROY Rself | 9 | 2012–2015 |
| FAROOQ MUKTA G | 8 | 2012–2015 |
| HANNON ROBERT | 8 | 2012–2015 |
| IYER SUBRAMANIAN S | 8 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 15 | 2002–2020 |