Inventor
Chulkyu Lee
Inventor
San Diego, CA, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication32%
G06FElectric digital data processing18%
H04BTransmission15%
H03KPulse technique8%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
H03MCoding3%
H03FAmplifiers2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
G01BMeasuring length, thickness or similar linear dimensions1%
PatentTitleYear
10,833,899Low power physical layer driver topologies202010,454,725C-PHY receiver equalization201910,419,252Low power physical layer driver topologies201910,389,315Three-input continuous-time amplifier and equalizer for multi-level signaling201910,333,690Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface201910,298,381Multiphase clock data recovery with adaptive tracking for a multi-wire, multi-phase interface201910,289,600Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols201910,263,766Independent pair 3-phase eye sampling circuit201910,127,167N-phase signal transition alignment201810,007,320Serializer and deserializer for odd ratio parallel data bus20189,998,300N-phase phase and polarity encoded serial interface20189,998,099Feed-forward bias circuit20189,998,154Low power physical layer driver topologies20189,971,392Serializer and deserializer for odd ratio parallel data bus20189,961,174Analog behavior modeling for 3-phase signaling20189,842,073'N-phase signal transition alignment'20179,819,523'Intelligent equalization for a three-transmitter multi-phase system'20179,762,228'High-speed programmable clock divider'20179,680,666'N-phase phase and polarity encoded serial interface'20179,673,969'Transcoding method for multi-wire signaling that embeds clock information in transition of signal state'20179,553,635'Time based equalization for a C-PHY 3-phase transmitter'20179,521,058'Multi-wire signaling with matched propagation delay among wire pairs'20169,496,879'Multiphase clock data recovery for a 3-phase interface'20169,485,080'Multiphase clock data recovery circuit calibration'20169,401,731'Skew control for three-phase communication'20169,369,237'Run-length detection and correction'20169,363,071'Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches'20169,337,997'Transcoding method for multi-wire signaling that embeds clock information in transition of signal state'20169,319,218'Multi-wire signaling with matched propagation delay among wire pairs'20169,313,058'Compact and fast N-factorial single data rate clock and data recovery circuits'20169,276,731'N-phase signal transition alignment'20169,231,790'N-phase phase and polarity encoded serial interface'20169,215,063'Specifying a 3-phase or N-phase eye pattern'20159,172,426'Voltage mode driver circuit for N-phase systems'20159,148,198'Programmable pre-emphasis circuit for MIPI C-PHY'20159,143,362'N-phase polarity output pin mode multiplexer'20159,137,008'Three phase clock recovery delay calibration'20159,130,735'Multi-phase clock generation method'20159,071,220'Efficient N-factorial differential signaling termination network'20158,996,740'N-phase polarity output pin mode multiplexer'20158,970,248'Sharing hardware resources between D-PHY and N-factorial termination networks'20158,746,056'Disdrometer system having a three-dimensional laser array unit'20148,619,762'Low power deserializer and demultiplexing method'20138,405,426'Method and apparatus to serialize parallel data input values'20137,956,642'Level shifter having low duty cycle distortion'20117,697,915'Gain boosting RF gain stage with cross-coupled capacitors'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2020Patents assigned to QUALCOMM INC (44)· patent assignee history
2010–2020Based in San Diego, CA, US· patent location history
2013–2014Patents assigned to LEE CHULKYU (3)· patent assignee history
2014Patents assigned to BAE JIN-YOUNG (1)· patent assignee history
2014Patents assigned to CHANG KI-HO (1)· patent assignee history
2014Patents assigned to CHOI YOUNG JEAN (1)· patent assignee history
2014Based in Seoul, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 44 | 2010–2020 |
| LEE CHULKYUself | 3 | 2013–2014 |
| BAE JIN-YOUNG | 1 | 2014 |
| CHANG KI-HO | 1 | 2014 |
| CHOI YOUNG JEAN | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Diego, California, US | 45 | 2010–2020 |
| Seoul, KR | 1 | 2014 |