Inventor

Ling-Yen Yeh

Inventor

Hsinchu, TW

Overview

1998–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 75 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H01LSemiconductor devices26%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%

H10BElectronic memory devices3%

B82YSpecific uses or applications of nanostructures2%

H03KPulse technique1%

C09KMaterials for miscellaneous applications, not provided for elsewhere0%

D01FChemical features in the manufacture of artificial filaments, threads, fibres, bristles or ribbons0%

D06NWall, floor, or like covering materials, e.g. linoleum, oilcloth, artificial leather, roofing felt, consisting of a fibrous web coated with a layer of macromolecular material0%

PatentTitleYear

11,043,556Local epitaxy nanofilms for nanowire stack GAA device2021 11,043,489Semiconductor device and manufacturing method thereof2021 10,879,394Semiconductor device and method of forming the same2020 10,872,822Method for manufacturing semiconductor devices2020 10,872,955Semiconductor device and fabricating method thereof2020 10,868,132Semiconductor device including standard cells with header/footer switch including negative capacitance2020 10,861,937Integrated circuit structure and method with solid phase diffusion2020 10,854,724One-dimensional nanostructure growth on graphene and devices thereof2020 10,825,899Semiconductor device and fabricating method thereof2020 10,825,933Gate-all-around structure and manufacturing method for the same2020 10,784,362Semiconductor device and manufacturing method thereof2020 10,770,592Multi-gate semiconductor device and method for forming the same2020 10,741,678Semiconductor device and manufacturing method thereof2020 10,741,646Field-effect transistors having contacts to 2D material active region2020 10,734,472Negative capacitance FET with improved reliability performance2020 10,727,230Integrated semiconductor device with 2D material layer2020 10,535,573System and method for test key characterizing wafer processing state2020 10,515,857Method for manufacturing semiconductor devices2019 10,516,061Semiconductor device and manufacturing method thereof2019 10,490,631Semiconductor device and fabricating method thereof2019 10,283,590Field-effect transistors having contacts to 2D material active region2019 10,276,697Negative capacitance FET with improved reliability performance2019 10,269,791Field-effect transistors having transition metal dichalcogenide channels and methods of manufacture2019 10,269,965Multi-gate semiconductor device and method for forming the same2019 10,269,666System and method for test key characterizing wafer processing state2019 10,186,602Fin structure of semiconductor device2019 10,164,016Integrated circuit structure and method with solid phase diffusion2018 10,164,033Conformal source and drain contacts for multi-gate field effect transistors2018 10,164,070Self-aligned passivation of active regions2018 10,141,454Field-effect transistors having black phosphorus channel and methods of making the same2018 10,134,865One-dimensional nanostructure growth on graphene and devices thereof2018 10,115,597Self-aligned dual-metal silicide and germanide formation2018 10,056,498Semiconductor device and manufacturing method thereof2018 10,043,908Contact structure of semiconductor device2018 10,032,889Self-aligned passivation of active regions2018 9,929,282'Field-effect transistors having black phosphorus channel and methods of making the same'2018 9,768,313'Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture'2017 9,716,146'Integrated circuit structure and method with solid phase diffusion'2017 9,711,607'One-dimensional nanostructure growth on graphene and devices thereof'2017 9,627,280'Methods for probing semiconductor fins through four-point probe and determining carrier concentrations'2017 9,620,627'Field-effect transistors having black phosphorus channel and methods of making the same'2017 9,614,086'Conformal source and drain contacts for multi-gate field effect transistors'2017 9,576,950'Contacts to transition metal dichalcogenide and manufacturing methods thereof'2017 9,559,182'Self-aligned dual-metal silicide and germanide formation'2017 9,553,025'Selective Fin-shaping process'2017 9,530,710'Passivation structure of fin field effect transistor'2016 9,525,049'Method for fabricating fin field effect transistors'2016 9,472,652'Fin structure of semiconductor device'2016 9,455,325'Fin field-effect transistors having controlled fin height'2016 9,431,288'System and method for test key characterizing wafer processing state'2016 9,412,847'Self-aligned passivation of active regions'2016 9,379,108'Contact structure of semiconductor device'2016 9,349,659'Methods for probing semiconductor fins and determining carrier concentrations therein'2016 9,337,285'Contact structure of semiconductor device'2016 9,257,343'Method for fabricating fin field effect transistors'2016 9,214,556'Self-aligned dual-metal silicide and germanide formation'2015 9,194,804'Stress analysis of 3-D structures using tip-enhanced Raman scattering technology'2015 9,142,474'Passivation structure of fin field effect transistor'2015 9,136,383'Contact structure of semiconductor device'2015 9,093,335'Calculating carrier concentrations in semiconductor Fins using probed resistance'2015 9,048,317'Contact structure of semiconductor device'2015 9,041,158'Method of forming fin field-effect transistors having controlled fin height'2015 8,963,257'Fin field effect transistors and methods for fabricating the same'2015 8,946,829'Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications'2015 8,168,501'Source/drain strained layers'2012 7,973,337'Source/drain strained layers'2011 7,851,328'STI stress modulation with additional implantation and natural pad sin mask'2010 7,781,799'Source/drain strained layers'2010 7,579,248'Resolving pattern-loading issues of SiGe stressor'2009 7,276,417'Hybrid STI stressor with selective re-oxidation anneal'2007 6,908,810'Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation'2005 6,835,622'Gate electrode doping method for forming semiconductor integrated circuit microelectronic fabrication with varying effective gate dielectric layer thicknesses'2004 5,889,309'Electrostatic discharge protection circuit'1999 5,760,631'Protection circuit for a CMOS integrated circuit'1998 5,714,255'Phosphorescent directional signals and manufacturing method'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2005Based in Taipei, TW· patent location history

1998Based in Anderson, SC, US· patent location history

2004–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (21)· patent assignee history

2007–2021Based in Hsinchu, TW· patent location history

2012–2015Patents assigned to YEH LING-YEN (5)· patent assignee history

2015Patents assigned to SHIH CHI-YUAN (4)· patent assignee history

2015Patents assigned to WANN CLEMENT HSINGJEN (4)· patent assignee history

2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (51)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	51	2016–2021
TAIWAN SEMICONDUCTOR MFG	21	2004–2016
YEH LING-YENself	5	2012–2015
SHIH CHI-YUAN	4	2015
WANN CLEMENT HSINGJEN	4	2015

Locations

Location	Patents	Span
Hsinchu, TW	70	2007–2021
Taipei, TW	4	1998–2005
Anderson, SC, US	1	1998