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Inventor

Nace Layadi

Inventor
Orlando, FL, US

Overview

26→
Patents
2001–2007
Patent span
Electricity
Primary field (CPC H)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1031%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10DInorganic electric semiconductor devices16%
H10BElectronic memory devices11%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
H01JElectric discharge tubes or discharge lamps5%
B24BMachines, devices, or processes for grinding or polishing4%
C23CCoating metallic material2%
C23FNon-mechanical removal of metallic material from surface2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
7,163,438'Zone polishing using variable slurry solid content'20076,984,166'Zone polishing using variable slurry solid content'20066,977,128'Multi-layered semiconductor structure'20056,910,907'Contact for use in an integrated circuit and a method of manufacture therefor'20056,821,886'IMP TiN barrier metal process'20046,730,600'Method of dry etching a semiconductor device in the absence of a plasma'20046,727,588'Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics'20046,720,604'Capacitor for an integrated circuit'20046,706,609'Method of forming an alignment feature in or on a multi-layered semiconductor structure'20046,656,850'Method for in-situ removal of side walls in MOM capacitor formation'20036,585,830'Method for cleaning tungsten from deposition wall chambers'20036,576,529'Method of forming an alignment feature in or on a multilayered semiconductor structure'20036,548,906'Method for reducing a metal seam in an interconnect structure and a device manufactured thereby'20036,472,307'Methods for improved encapsulation of thick metal features in integrated circuit fabrication'20026,458,648'Method for in-situ removal of side walls in MOM capacitor formation'20026,436,829'Two phase chemical/mechanical polishing process for tungsten layers'20026,406,999'Semiconductor device having reduced line width variations between tightly spaced and isolated features'20026,395,639'Process for improving line width variations between tightly spaced and isolated features in integrated circuits'20026,358,790'Method of making a capacitor'20026,323,537'Capacitor for an integrated circuit'20016,258,610'Method analyzing a semiconductor surface using line width metrology with auto-correlation operation'20016,249,016'Integrated circuit capacitor including tapered plug'20016,218,085'Process for photoresist rework to avoid sodium incorporation'20016,218,255'Method of making a capacitor'20016,204,186'Method of making integrated circuit capacitor including tapered plug'20016,180,518'Method for forming vias in a low dielectric constant material'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2002Patents assigned to AGERE SYST GUARDIAN CORP (10)· patent assignee history
2001Patents assigned to LUCENT TECHNOLOGIES INC (3)· patent assignee history
2001–2004Based in Orlando, FL, US· patent location history
2002–2007Based in Singapore, SG· patent location history
2003–2005Patents assigned to AGERE SYSTEMS INC (10)· patent assignee history
2004–2007Patents assigned to CHARTERED SEMICONDUCTOR MFG (3)· patent assignee history
2004Patents assigned to ELITH LLC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
AGERE SYST GUARDIAN CORP102001–2002
AGERE SYSTEMS INC102003–2005
CHARTERED SEMICONDUCTOR MFG32004–2007
LUCENT TECHNOLOGIES INC32001
ELITH LLC12004
Locations
LocationPatentsSpan
Orlando, Florida, US152001–2004
Singapore, SG112002–2007