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Inventor

Richard C. Foss

Inventor
Kirkcaldy, GB

Overview

65→
Patents
1983–2014
Patent span
Physics
Primary field (CPC G)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores42%
H03KPulse technique14%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses8%
G05FSystems for regulating electric or magnetic variables7%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems7%
G06FElectric digital data processing5%
G10HElectrophonic musical instruments3%
H04HBroadcast communication3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H04NPictorial communication, e.g. television3%
PatentTitleYear
8,862,755'Apparatus and a method for modifying a command message in a digital multimedia network'20148,855,008'Digital multimedia network with parameter join mechanism'20148,638,638'Delay locked loop implementation in a synchronous dynamic random access memory'20148,571,045'Data stream router'20138,477,812'Digital multimedia network with latency control'20138,441,878'Embedded memory databus architecture'20138,369,182'Delay locked loop implementation in a synchronous dynamic random access memory'20138,218,386'Embedded memory databus architecture'20127,859,930'Embedded memory databus architecture'20107,636,880'Error correction scheme for memory'20097,609,573'Embedded memory databus architecture'20097,599,246'Delay locked loop implementation in a synchronous dynamic random access memory'20097,486,580'Wide databus architecture'2009RE040552'Dynamic random access memory using imperfect isolating transistors'20087,350,137'Method and circuit for error correction in CAM cells'20087,266,747'Error correction scheme for memory'20077,095,666'Wide databus architecture'20067,010,741'Method and circuit for error correction in CAM cells'20066,992,950'Delay locked loop implementation in a synchronous dynamic random access memory'20066,980,448'DRAM boosted voltage supply'20056,888,730'Content addressable memory cell'20056,888,731'Method and apparatus for replacing defective rows in a semiconductor memory array'20056,873,532'Content addressable memory cell having improved layout'20056,751,111'High density memory cell'20046,661,723'Wide databus architecture'20036,657,918'Delayed locked loop implementation in a synchronous dynamic random access memory'20036,657,919'Delayed locked loop implementation in a synchronous dynamic random access memory'20036,614,705'Dynamic random access memory boosted voltage supply'20036,580,652'Priority encoder circuit and method for content addressable memory'20036,580,654'Boosted voltage supply'20036,522,562'Content addressable memory cell having improved layout'2003RE037641'Dynamic random access memory using imperfect isolating transistors'20026,366,491'Wide databus architecture'20026,314,052'Delayed locked loop implementation in a synchronous dynamic random access memory'20016,236,581'High voltage boosted word line supply charge pump and regulator for DRAM'20016,205,083'Delayed locked loop implementation in a synchronous dynamic random access memory'20016,195,282'Wide database architecture'20016,067,272'Delayed locked loop implementation in a synchronous dynamic random access memory'20006,055,201'High voltage boosted word line supply charge pump and regulator for DRAM'20005,870,329'Enhanced ASIC process cell'19995,844,916'Built in access time comparator'19985,828,620'High voltage boosted word line supply charge pump and regulator for DRAM'19985,822,333'Digital memory testing method'19985,796,673'Delay locked loop implementation in a synchronous dynamic random access memory'19985,742,544'Wide databus architecture'19985,724,304'Repeater with threshold modulation'19985,703,508'Repeater with threshold modulation'19975,699,313'High voltage boosted word line supply charge pump and regulator for dram'19975,576,649'Repeater with threshold modulation'19965,574,681'Method for DRAM sensing current control'19965,497,115'Flip-flop circuit having low standby power for driving synchronous dynamic random access memory'19965,414,662'Dynamic random access memory using imperfect isolating transistors'19955,406,523'High voltage boosted word line supply charge pump and regulator for DRAM'19955,267,201'High voltage boosted word line supply charge pump regulator for DRAM'19935,255,232'DRAM cell plate and precharge voltage generator'19935,245,576'Dynamic memory row/column redundancy scheme'19935,233,560'Dynamic memory bit line precharge scheme'19935,093,808'Folded bitline dynamic RAM with reduced shared supply voltages'19925,042,012'Serial access dynamic ram'19915,027,329'Addressing for large dynamic RAM'19915,014,244'Integrated memory circuit with parallel and serial input and output'19914,980,862'Folded bitline dynamic ram with reduced shared supply voltages'19904,789,796'Output buffer having sequentially-switched output'19884,786,830'CMOS input buffer circuit for TTL signals'19884,367,420'Dynamic logic circuits operating in a differential mode for array processing'1983

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–1993Patents assigned to MOSAID INC (6)· patent assignee history
1990–2014Based in Calabogie, CA· patent location history
1991–2009Based in Kirkcaldy, GB· patent location history
1993–2013Patents assigned to FOSS RICHARD C (5)· patent assignee history
1995–2014Patents assigned to MOSAID TECHNOLOGIES INC (47)· patent assignee history
1998–2013Based in Scotland, GB· patent location history
2003–2005Based in Fife, GB· patent location history
2013–2014Patents assigned to FOSS RICHARD (4)· patent assignee history
2013–2014Patents assigned to GURDAN ROBBY (4)· patent assignee history
2013–2014Based in Grahamstown, ZA· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MOSAID TECHNOLOGIES INC471995–2014
MOSAID INC61990–1993
FOSS RICHARD Cself51993–2013
FOSS RICHARDself42013–2014
GURDAN ROBBY42013–2014
Locations
LocationPatentsSpan
Kirkcaldy, GB251991–2009
Calabogie, CA161990–2014
Scotland, GB71998–2013
Fife, GB62003–2005
Grahamstown, ZA42013–2014