Inventor
Chih-Ning Wu
Inventor
Hsinchu, TW
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1038%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%
H10DInorganic electric semiconductor devices17%
C23GCleaning or de-greasing of metallic material by chemical methods other than electrolysis6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
B01DSeparation2%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry2%
B82YSpecific uses or applications of nanostructures2%
C23FNon-mechanical removal of metallic material from surface2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
7,595,234'Fabricating method for a metal oxide semiconductor transistor'20097,544,621'Method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process and etching method'20097,491,615'Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors'20097,338,910'Method of fabricating semiconductor devices and method of removing a spacer'20087,220,647'Method of cleaning wafer and method of manufacturing gate structure'20077,214,988'Metal oxide semiconductor transistor'20077,196,019'Method of removing spacers and fabricating MOS transistor'20077,172,976'Extrusion-free wet cleaning process for copper-dual damascene structures'20077,135,400'Damascene process capable of avoiding via resist poisoning'20066,794,292'Extrusion-free wet cleaning process for copper-dual damascene structures'20046,780,761'Via-first dual damascene process'20046,767,825'Etching process for forming damascene structure of the semiconductor'20046,733,597'Method of cleaning a dual damascene structure'20046,692,580'Method of cleaning a dual damascene structure'20046,635,565'Method of cleaning a dual damascene structure'20036,554,002'Method for removing etching residues'20036,511,916'Method for removing the photoresist layer in the damascene process'20036,495,472'Method for avoiding erosion of conductor structure during removing etching residues'20026,453,915'Post polycide gate etching cleaning method'20026,440,873'Post metal etch cleaning method'20026,303,482'Method for cleaning the surface of a semiconductor wafer'20016,060,415'Aligned molecular sieve crystals grown on anodic alumina membrane'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000Patents assigned to NAT SCIENCE COUNCIL (1)· patent assignee history
2000Based in Taipei, TW· patent location history
2001–2009Patents assigned to UNITED MICROELECTRONICS CORP (20)· patent assignee history
2001Based in Hsin Chu, TW· patent location history
2002Patents assigned to UNITED MICROELECTRONICS CORPS (1)· patent assignee history
2002–2009Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNITED MICROELECTRONICS CORP | 20 | 2001–2009 |
| NAT SCIENCE COUNCIL | 1 | 2000 |
| UNITED MICROELECTRONICS CORPS | 1 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 20 | 2002–2009 |
| Hsin Chu, TW | 1 | 2001 |
| Taipei, TW | 1 | 2000 |