Inventor
Rajesh Sankaran Madukkarumukumana
Inventor
Portland, OR, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing81%
H04LTransmission of digital information, e.g. telegraphic communication19%
PatentTitleYear
10,114,767Virtualizing physical memory in a virtual machine system using a hierarchy of extended page tables to translate guest-physical addresses to host-physical addresses20189,892,069'Posting interrupts to virtual processors'20189,442,868'Delivering interrupts directly to a virtual processor'20169,164,920'Using permission bits in translating guests virtual addresses to guest physical addresses to host physical addresses'20159,116,869'Posting interrupts to virtual processors'20158,938,737'Delivering interrupts directly to a virtual processor'20158,850,098'Direct memory access (DMA) address translation between peer input/output (I/O) devices'20148,843,683'Posting interrupts to virtual processors'20148,843,727'Performance enhancement of address translation using translation tables covering large address spaces'20148,706,942'Direct memory access (DMA) address translation between peer-to-peer input/output (I/O) devices'20148,645,665'Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses'20148,566,492'Posting interrupts to virtual processors'20138,533,428'Translating a guest virtual address to a host physical address as guest software executes on a virtual machine'20138,286,162'Delivering interrupts directly to a virtual processor'20127,984,203'Address window support for direct memory access translation'20117,937,534'Performing direct cache access transactions based on a memory access data structure'20117,886,126'Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system'20117,814,496'Method and system for replicating schedules with regard to a host controller for virtualization'20107,757,231'System and method to deprivilege components of a virtual machine monitor'20107,702,826'Method and apparatus by utilizing platform support for direct memory access remapping by remote DMA (“RDMAâ€)-capable devices'20107,506,121'Method and apparatus for a guest to access a memory mapped device'20097,467,381'Resource partitioning and direct access utilizing hardware support for virtualization'20087,451,197'Method, system, and article of manufacture for network protocols'20087,406,583'Autonomic computing utilizing a sequestered processing resource on a host CPU'20087,400,639'Method, system, and article of manufacture for utilizing host memory from an offload adapter'20087,340,582'Fault processing for direct memory access address translation'20087,334,107'Caching support for direct memory access address translation'20087,222,203'Interrupt redirection for virtual partitioning'20077,103,683'Method, apparatus, system, and article of manufacture for processing control data by an offload adapter'20066,460,080'Credit based flow control scheme over virtual interface architecture for system area networks'20026,347,337'Credit based flow control scheme over virtual interface architecture for system area networks'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2018Patents assigned to INTEL CORP (30)· patent assignee history
2002Based in Beaverton, OR, US· patent location history
2006–2018Based in Portland, OR, US· patent location history
2008Based in Hillsboro, OR, US· patent location history
2011–2015Patents assigned to MADUKKARUMUKUMANA RAJESH SANKARAN (6)· patent assignee history
2012–2015Patents assigned to NEIGER GILBERT (6)· patent assignee history
2012–2015Patents assigned to ANDERSON ANDREW V (4)· patent assignee history
2013–2014Patents assigned to UHLIG RICHARD (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 30 | 2002–2018 |
| MADUKKARUMUKUMANA RAJESH SANKARANself | 6 | 2011–2015 |
| NEIGER GILBERT | 6 | 2012–2015 |
| UHLIG RICHARD | 5 | 2013–2014 |
| ANDERSON ANDREW V | 4 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 28 | 2006–2018 |
| Beaverton, OR, US | 2 | 2002 |
| Hillsboro, OR, US | 1 | 2008 |