Inventor
SCOTT JANUS
Inventor
US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Tprimary
G06TImage data processing or generation, in general29%
G06FElectric digital data processing25%
G06NComputing arrangements based on specific computational models16%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
H03MCoding6%
B60KArrangement or mounting of propulsion units or of transmissions in vehicles3%
B60RVehicles, vehicle fittings, or vehicle parts, not otherwise provided for3%
G02BOptical elements, systems or apparatus3%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
H04NPictorial communication, e.g. television3%
PatentTitleYear
12,572,997Graphics processing unit processing and caching improvements202612,554,674Multi-tile memory management202612,493,922Graphics processing unit processing and caching improvements202512,450,780Multi-plane image compression202512,370,453Anti-cheat game technology in graphics hardware202512,293,431Sparse optimizations for a matrix accelerator architecture202512,243,496Glare and occluded view compensation for automotive and other applications202512,229,867Graphics architecture including a neural network pipeline202512,210,477Systems and methods for improving cache efficiency and utilization202512,182,035Systems and methods for cache optimization202412,182,062Multi-tile memory management202412,147,302Systems and methods for error detection and control for embedded memory and compute elements202412,124,383Systems and methods for cache optimization202412,124,533Method and apparatus of spatially sparse convolution module for visual rendering and synthesis202412,099,461Multi-tile memory management202412,094,048Multi-tile graphics processor rendering202412,079,155Graphics processor operation scheduling for deterministic latency202412,056,059Systems and methods for cache optimization202412,013,808Multi-tile architecture for graphics operations202411,989,815Cluster of scalar engines to accelerate intersection in leaf node202411,892,950Data prefetching for graphics data processing202411,880,928Apparatus and method for a hierarchical beam tracer202411,861,761Graphics processing unit processing and caching improvements202411,699,404Glare and occluded view compensation for automotive and other applications202311,676,239Sparse optimizations for a matrix accelerator architecture202311,676,322Graphics architecture including a neural network pipeline202311,627,307Transport controlled video coding202311,620,256Systems and methods for improving cache efficiency and utilization202311,557,085Neural network processing for multi-object 3D modeling202311,409,658Data prefetching for graphics data processing202211,322,099Glare and occluded view compensation for automotive and other applications202211,315,304Apparatus and method for a hierarchical beam tracer202211,284,118Surface normal vector processing mechanism202211,263,799Cluster of scalar engines to accelerate intersection in leaf node202211,151,769Graphics architecture including a neural network pipeline202111,145,105Multi-tile graphics processor rendering2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (36)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 36 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 36 | 2021–2026 |