Inventor
John W. Ward, III
Inventor
Pflugerville, TX, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
9,342,307'Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions'20169,069,546'Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions'20158,661,230'Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions'20148,145,885'Apparatus for randomizing instruction thread interleaving in a multi-thread processor'20127,827,388'Apparatus for adjusting instruction thread priority in a multi-thread processor'20107,822,954'Methods, systems, and computer program products for recovering from branch prediction latency'20107,769,984'Dual-issuance of microprocessor instructions using dual dependency matrices'20107,549,095'Error detection enhancement in a microprocessor through the use of a second dependency matrix'20097,487,334'Branch encoding before instruction cache write'20097,475,223'Fetch-side instruction dispatch group formation'20097,469,407'Method for resource balancing using dispatch flush in a simultaneous multithread processor'20087,401,207'Apparatus and method for adjusting instruction thread priority in a multi-thread processor'20087,401,208'Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor'20087,360,062'Method and apparatus for selecting an instruction thread for processing in a multi-thread processor'20087,305,586'Accessing and manipulating microprocessor state'20077,269,715'Instruction grouping history on fetch-side dispatch group formation'20077,213,135'Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditions'20077,013,400'Method for managing power in a simultaneous multithread processor by loading instructions into pipeline circuit during select times based on clock signal frequency and selected power mode'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2016Patents assigned to IBM (18)· patent assignee history
2006–2016Based in Pflugerville, TX, US· patent location history
2012Patents assigned to KALLA RONALD NICK (1)· patent assignee history
2014–2015Patents assigned to ALEXANDER GREGORY W (2)· patent assignee history
2014–2015Patents assigned to BARRICK BRIAN D (2)· patent assignee history
2014–2015Patents assigned to WARD III JOHN W (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 2006–2016 |
| ALEXANDER GREGORY W | 2 | 2014–2015 |
| BARRICK BRIAN D | 2 | 2014–2015 |
| WARD III JOHN Wself | 2 | 2014–2015 |
| KALLA RONALD NICK | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Pflugerville, Texas, US | 18 | 2006–2016 |