Inventor
Yan Solihin
Inventor
Raleigh, NC, US
Overview
Patents· 56 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing50%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use27%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications10%
G11CStatic stores7%
H04LTransmission of digital information, e.g. telegraphic communication5%
H04WWireless communication networks1%
PatentTitleYear
10,956,331Cache partitioning in a multicore processor202110,445,287Circuit switch pre-reservation in an on-chip network201910,445,131Core prioritization for heterogeneous on-chip networks201910,346,227Increased refresh interval and energy efficiency in a DRAM201910,346,308Cache partitioning in a multicore processor201910,289,452Thread and data assignment in multi-core processors based on cache miss data and thread category201910,176,107Methods and systems for dynamic DRAM cache sizing201910,152,410Magnetoresistive random-access memory cache write management201810,007,605Hardware-based array compression20189,990,293Energy-efficient dynamic dram cache sizing via selective refresh of a cache in a dram20189,965,385Memory allocation accelerator20189,946,647Directory coherence for multicore processors20189,916,255'Data storage based on memory persistency'20189,858,111'Heterogeneous magnetic memory architecture'20189,846,627Systems and methods for modeling memory access behavior and memory traffic timing behavior20179,772,950'Multi-granular cache coherence'20179,766,681'Operations related to a retransmission buffer'20179,760,486'Accelerating cache state transfer on a directory-based multicore architecture'20179,710,303'Shared cache data movement in thread migration'20179,684,603'Memory initialization using cache state'20179,678,550'Dynamic router power control in multi-core processors'20179,632,832'Thread and data assignment in multi-core processors based on cache miss data'20179,612,961'Cache partitioning in a multicore processor'20179,564,202'Increased refresh interval and energy efficiency in a DRAM'20179,552,295'Performance and energy efficiency while using large pages'20179,501,350'Detecting unidirectional resistance drift errors in a multilevel cell of a phase change memory'20169,473,426'Hybrid routers in multicore architectures'20169,471,381'Resource allocation in multi-core architectures'20169,465,729'Memory allocation accelerator'20169,411,693'Directory error correction in multi-core processor architectures'20169,391,927'Heterogeneous router clock assignment and packet routing'20169,342,305'Low power execution of a multithreaded program'20169,336,146'Accelerating cache state transfer on a directory-based multicore architecture'20169,304,946'Hardware-base accelerator for managing copy-on-write of multi-level caches utilizing block copy-on-write differential update table'20169,304,898'Hardware-based array compression'20169,275,696'Energy conservation in a multicore chip'20169,251,072'Cache coherence directory in multi-processor architectures'20169,229,865'One-cacheable multi-core architecture'20169,207,980'Balanced processing using heterogeneous cores'20159,166,930'Waved time multiplexing'20159,158,689'Aggregating cache eviction notifications to a directory'20159,098,406'Managing addressable memory in heterogeneous multicore processors'20159,053,057'Cache coherence directory in multi-processor architectures'20159,047,194'Virtual cache directory in multi-processor architectures'20159,047,137'Balanced processing using heterogeneous cores'20158,990,828'Resource allocation in multi-core architectures'20158,924,754'Quality of service targets in multicore processors'20148,874,849'Sectored cache with a tag structure capable of tracking sectors of data stored for a particular cache way'20148,868,800'Accelerator buffer access'20148,832,414'Dynamically determining the profitability of direct fetching in a multicore architecture'20148,667,227'Domain based cache coherence protocol'20148,615,633'Multi-core processor cache coherence for reduced off-chip traffic'20138,589,933'Low power execution of a multithreaded program'20138,407,426'Data storage and access in multi-core processor architectures'20138,244,986'Data storage and access in multi-core processor architectures'20128,195,888'Multiprocessor cache prefetch with off-chip bandwidth allocation'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2021Patents assigned to EMPIRE TECHNOLOGY DEV LLC (55)· patent assignee history
2012–2016Patents assigned to SOLIHIN YAN (19)· patent assignee history
2012–2018Based in Apex, NC, US· patent location history
2014–2021Based in Raleigh, NC, US· patent location history
2016Based in Poway, CA, US· patent location history
2017Patents assigned to UNIV NORTH CAROLINA STATE (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| EMPIRE TECHNOLOGY DEV LLC | 55 | 2012–2021 |
| SOLIHIN YANself | 19 | 2012–2016 |
| UNIV NORTH CAROLINA STATE | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Raleigh, NC, US | 39 | 2014–2021 |
| Apex, NC, US | 16 | 2012–2018 |
| Poway, California, US | 1 | 2016 |