Inventor

Yelehanka Ramachandramurthy Pradeep

Inventor

Singapore, SG

Overview

1999–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 59 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices46%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

B24BMachines, devices, or processes for grinding or polishing2%

H01FMagnets2%

C23CCoating metallic material1%

G02BOptical elements, systems or apparatus1%

H01JElectric discharge tubes or discharge lamps1%

H01LSemiconductor devices1%

PatentTitleYear

9,633,882'Integrated circuits with alignment marks and methods of producing the same'2017 8,293,545'Critical dimension for trench and vias'2012 7,382,027'MOSFET device with low gate contact resistance'2008 6,861,317'Method of making direct contact on gate by using dielectric stop layer'2005 6,852,605'Method of forming an inductor with continuous metal deposition'2005 6,821,904'Method of blocking nitrogen from thick gate oxide during dual gate CMP'2004 6,791,083'Image compensation device for a scanning electron microscope'2004 6,726,545'Linear polishing for improving substrate uniformity'2004 6,716,693'Method of forming a surface coating layer within an opening within a body by atomic layer deposition'2004 6,709,934'Method for forming variable-K gate dielectric'2004 6,660,642'Toxic residual gas removal by non-reactive ion sputtering'2003 6,632,745'Method of forming almost L-shaped spacer for improved ILD gap fill'2003 6,566,208'Method to form elevated source/drain using poly spacer'2003 6,544,824'Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel'2003 6,541,327'Method to form self-aligned source/drain CMOS device on insulated staircase oxide'2003 6,511,884'Method to form and/or isolate vertical transistors'2003 6,468,877'Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner'2002 6,468,853'Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner'2002 6,461,887'Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth'2002 6,461,900'Method to form a self-aligned CMOS inverter using vertical device integration'2002 6,455,377'Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)'2002 6,451,704'Method for forming PLDD structure with minimized lateral dopant diffusion'2002 6,440,800'Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers'2002 6,436,770'Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation'2002 6,436,774'Method for forming variable-K gate dielectric'2002 6,417,056'Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge'2002 6,417,054'Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide'2002 6,406,945'Method for forming a transistor gate dielectric with high-K and low-K regions'2002 6,403,485'Method to form a low parasitic capacitance pseudo-SOI CMOS device'2002 6,399,448'Method for forming dual gate oxide'2002 6,387,765'Method for forming an extended metal gate using a damascene process'2002 6,380,088'Method to form a recessed source drain on a trench side wall with a replacement gate technique'2002 6,355,581'Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability'2002 6,346,468'Method for forming an L-shaped spacer using a disposable polysilicon spacer'2002 6,337,262'Self aligned T-top gate process integration'2002 6,316,304'Method of forming spacers of multiple widths'2001 6,313,008'Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon'2001 6,312,999'Method for forming PLDD structure with minimized lateral dopant diffusion'2001 6,306,714'Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide'2001 6,306,715'Method to form smaller channel with CMOS device by isotropic etching of the gate materials'2001 6,303,447'Method for forming an extended metal gate using a damascene process'2001 6,303,449'Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP'2001 6,300,177'Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials'2001 6,300,251'Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon'2001 6,294,480'Method for forming an L-shaped spacer with a disposable organic top coating'2001 6,284,613'Method for forming a T-gate for better salicidation'2001 6,281,093'Method to reduce trench cone formation in the fabrication of shallow trench isolations'2001 6,277,716'Method of reduce gate oxide damage by using a multi-step etch process with a predictable premature endpoint system'2001 6,277,700'High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness'2001 6,277,683'Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer'2001 6,251,764'Method to form an L-shaped silicon nitride sidewall spacer'2001 6,248,006'CMP uniformity'2001 6,228,770'Method to form self-sealing air gaps between metal interconnects'2001 6,228,713'Self-aligned floating gate for memory application using shallow trench isolation'2001 6,211,008'Method for forming high-density high-capacity capacitor'2001 6,200,887'Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits'2001 6,156,598'Method for forming a lightly doped source and drain structure using an L-shaped spacer'2000 5,866,448'Procedure for forming a lightly-doped-drain structure using polymer layer'1999 5,858,847'Method for a lightly doped drain structure'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2008Patents assigned to CHARTERED SEMICONDUCTOR MFG (57)· patent assignee history

1999–2017Based in Singapore, SG· patent location history

2002Patents assigned to INST OF MICROELECTRONICS (1)· patent assignee history

2012–2017Patents assigned to GLOBALFOUNDRIES SG PTE LTD (2)· patent assignee history

2012Patents assigned to CONG HAI (1)· patent assignee history

2012Patents assigned to HSIA LIANG CHOO (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
CHARTERED SEMICONDUCTOR MFG	57	1999–2008
GLOBALFOUNDRIES SG PTE LTD	2	2012–2017
CONG HAI	1	2012
HSIA LIANG CHOO	1	2012
INST OF MICROELECTRONICS	1	2002

Locations

Location	Patents	Span
Singapore, SG	59	1999–2017