Inventor
Kourosh Gharachorloo
Inventor
Menlo Park, CA, US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing75%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
H04LTransmission of digital information, e.g. telegraphic communication8%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes6%
G05BControl or regulating systems in general2%
PatentTitleYear
10,257,208Method and system for using a network analysis system to verify content on a website20198,762,280'Method and system for using a network analysis system to verify content on a website'20147,523,016'Detecting anomalies'20097,502,895'Techniques for reducing castouts in a snoop filter'20097,467,131'Method and system for query data caching and optimization in a search engine system'20087,389,389'System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system'20087,254,580'System and method for selectively searching partitions of a database'20077,174,346'System and method for searching an extended database'20077,152,191'Fault containment and error recovery in a scalable multiprocessor'20066,988,170'Scalable architecture based on single-chip multiprocessing'20066,925,537'Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants'20056,918,015'Scalable directory based cache coherence protocol'20056,912,624'Method and system for exclusive two-level caching in a chip-multiprocessor'20056,751,720'Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy'20046,751,710'Scalable multiprocessor system and cache coherence method'20046,748,498'Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector'20046,738,868'System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes'20046,725,343'System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system'20046,725,334'Method and system for exclusive two-level caching in a chip-multiprocessor'20046,697,919'System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system'20046,678,840'Fault containment and error recovery in a scalable multiprocessor'20046,675,265'Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants'20046,668,308'Scalable architecture based on single-chip multiprocessing'20036,640,287'Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests'20036,636,949'System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing'20036,633,960'Scalable directory based cache coherence protocol'20036,622,217'Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system'20036,622,218'Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system'20036,412,056'Extended translation lookaside buffer with fine-grain state bits'20026,286,090'Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches'20016,209,065'Mechanism for optimizing generation of commit-signals in a distributed shared-memory system'20016,108,737'Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system'20006,101,420'Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories'20006,088,771'Mechanism for reducing latency of memory barrier operations on a multiprocessor system'20006,085,263'Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor'20006,055,605'Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches'20005,950,228'Variable-grained memory sharing for clusters of symmetric multi-processors using private and shared state tables'19995,933,598'Method for sharing variable-grained memory of workstations by sending particular block including line and size of the block to exchange shared data structures'19995,787,480'Lock-up free data sharing'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2000Patents assigned to DIGITAL EQUIPMENT CORP (4)· patent assignee history
1998–2001Based in Stanford, CA, US· patent location history
1999–2019Based in Menlo Park, CA, US· patent location history
2000–2001Patents assigned to COMPAQ COMPUTER CORP (6)· patent assignee history
2000Based in Standford, CA, US· patent location history
2003–2009Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (22)· patent assignee history
2007–2014Patents assigned to GOOGLE INC (5)· patent assignee history
2014Patents assigned to AGRAWAL SHRISH (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HEWLETT PACKARD DEVELOPMENT CO | 22 | 2003–2009 |
| COMPAQ COMPUTER CORP | 6 | 2000–2001 |
| GOOGLE INC | 5 | 2007–2014 |
| DIGITAL EQUIPMENT CORP | 4 | 1998–2000 |
| AGRAWAL SHRISH | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Menlo Park, California, US | 30 | 1999–2019 |
| Stanford, California, US | 8 | 1998–2001 |
| Standford, California, US | 1 | 2000 |