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Inventor

Paul Alan McConnelee

Inventor
Albany, NY, US

Overview

61→
Patents
1980–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 61 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1040%
H01LSemiconductor devices21%
H05KPrinted circuits10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
Y10TTechnical subjects covered by former us classification4%
B29CShaping or joining of plastics2%
H10DInorganic electric semiconductor devices2%
H10KOrganic electric solid-state devices2%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds1%
C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients1%
PatentTitleYear
10,607,957Ultra-thin embedded semiconductor device package and method of manufacturing thereof202010,453,786Power electronics package and method of manufacturing thereof201910,276,486Stress resistant micro-via structure for flexible circuits201910,269,688Power overlay structure and method of making same201910,204,881Power overlay structure and reconstituted semiconductor wafer having wirebonds201910,186,477Power overlay structure and method of making same201910,141,203Electrical interconnect structure for an embedded electronics package201810,141,251Electronic packages with pre-defined via patterns and methods of making and using the same201810,068,840Electrical interconnect for an integrated circuit package and method of making same20189,953,917Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof20189,953,913Electronics package with embedded through-connect structure and method of manufacturing thereof20189,847,236Electrical interconnect structure for an embedded electronics package20179,806,051'Ultra-thin embedded semiconductor device package and method of manufacturing thereof'20179,704,788'Power overlay structure and method of making same'20179,679,837'Electrical interconnect for an integrated circuit package and method of making same'20179,653,438'Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof'20179,613,843'Power overlay structure having wirebonds and method of manufacturing same'20179,613,932'Integrated circuit package and method of making same'20179,570,376'Electrical interconnect for an integrated circuit package and method of making same'20179,391,027'Embedded semiconductor device package and method of manufacturing thereof'20169,299,630'Diffusion barrier for surface mount modules'20169,299,647'Electrical interconnect for an integrated circuit package and method of making same'20169,236,348'Ultrathin buried die module and method of manufacturing thereof'20169,209,151'Embedded semiconductor device package and method of manufacturing thereof'20159,184,124'Reliable surface mount integrated power module'20159,171,785'Power overlay structure with leadframe connections'20159,165,864'Power overlay structure with leadframe connections'20159,117,813'Integrated circuit package and method of making same'20158,987,876'Power overlay structure and method of making same'20158,941,208'Reliable surface mount integrated power module'20158,829,690'System of chip package build-up'20148,742,558'Component protection for advanced packaging applications'20148,704,211'High integrity protective coatings'20148,691,371'Barrier coating and method'20148,658,473'Ultrathin buried die module and method of manufacturing thereof'20148,653,635'Power overlay structure with leadframe connections'20148,653,670'Electrical interconnect for an integrated circuit package and method of making same'20148,629,003'Epoxy encapsulating and lamination adhesive and method of making same'20148,623,699'Method of chip package build-up'20148,586,421'Method of forming semiconductor device package having high breakdown voltage and low parasitic inductance'20138,466,007'Power semiconductor module and fabrication method'20138,431,444'Epoxy encapsulating and lamination adhesive and method of making same'20138,334,593'Semiconductor device package'20128,310,040'Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof'20128,114,712'Method for fabricating a semiconductor device package'20128,114,708'System and method for pre-patterned embedded chip build-up'20128,049,338'Power semiconductor module and fabrication method'20118,008,781'Apparatus and method for reducing pitch in an integrated circuit'20118,008,125'System and method for stacked die embedded chip build-up'20117,976,899'Methods for selective deposition of graded materials on continuously fed objects'20117,964,974'Electronic chip package with reduced contact pad pitch'20116,737,002'Fabrication of plastic module with exposed backside contact'20046,515,417'Organic light emitting device and method for mounting'20036,377,461'Power electronic module packaging'20026,232,151'Power electronic module packaging'20016,146,558'Structure and method for molding optical disks'20005,950,303'Method and fixturing to perform two side laminations of stacked substrates forming 3-D modules'19995,774,326'Multilayer capacitors using amorphous hydrogenated carbon'19985,576,925'Flexible multilayer thin film capacitors'19965,285,571'Method for extending an electrical conductor over an edge of an HDI substrate'19944,227,944'Methods of making composite conductive structures in integrated circuits'1980

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1980–2020Patents assigned to GEN ELECTRIC (59)· patent assignee history
1980–2014Based in Schenectady, NY, US· patent location history
2011–2020Based in Albany, NY, US· patent location history
2012–2019Patents assigned to MCCONNELEE PAUL ALAN (17)· patent assignee history
2012–2016Patents assigned to GOWDA ARUN VIRUPAKSHA (9)· patent assignee history
2012–2019Patents assigned to GORCZYCA THOMAS BERT (6)· patent assignee history
2013–2014Patents assigned to DUROCHER KEVIN MATTHEW (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
GEN ELECTRIC591980–2020
MCCONNELEE PAUL ALANself172012–2019
GOWDA ARUN VIRUPAKSHA92012–2016
GORCZYCA THOMAS BERT62012–2019
DUROCHER KEVIN MATTHEW42013–2014
Locations
LocationPatentsSpan
Albany, New York, US452011–2020
Schenectady, New York, US161980–2014