Inventor
Akira Takamatsu
Inventor
Hamura, JP
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H10BElectronic memory devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
C25DProcesses for the electrolytic or electrophoretic production of coatings4%
B05BSpraying apparatus2%
B05CApparatus for applying fluent materials to surfaces, in general2%
B05DProcesses for applying fluent materials to surfaces, in general2%
B23KSoldering or unsoldering2%
PatentTitleYear
10,006,143Power supplying member and high-speed plating machine provided with the same201810,006,137Holding device and high-speed plating machine provided with the same20187,402,473'Semiconductor device and process for producing the same'20087,397,104'Semiconductor integrated circuit device and a method of manufacturing the same'20087,208,391'Method of manufacturing a semiconductor integrated circuit device that includes forming an isolation trench around active regions and filling the trench with two insulating films'20077,074,691'Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating material'20067,060,589'Method for manufacturing a semiconductor integrated circuit device that includes covering the bottom of an isolation trench with spin-on glass and etching back the spin-on glass to a predetermined depth'20066,881,646'Semiconductor device and process for producing the same'20056,720,234'Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing'20046,717,202'HSG semiconductor capacitor with migration inhibition layer'20046,693,008'Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device'20046,562,695'Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing'20036,559,027'Semiconductor device and process for producing the sme'20036,524,927'Semiconductor device and method of fabricating the same'20036,242,323'Semiconductor device and process for producing the same'20016,057,241'Method of manufacturing a semiconductor integrated circuit device'20005,951,885'Method and apparatus for generating welding pressure in a roller seam welding machine'19994,869,201'Apparatus for coating can barrels'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989Based in Iwatsuki, JP· patent location history
1999Based in Saitama, JP· patent location history
2000–2008Patents assigned to HITACHI ULSI SYS CO LTD (11)· patent assignee history
2000–2004Patents assigned to HITACHI LTD (6)· patent assignee history
2000–2008Based in Hamura, JP· patent location history
2004–2008Patents assigned to RENESAS TECH CORP (4)· patent assignee history
2018Patents assigned to KYB CORP (2)· patent assignee history
2018Patents assigned to CHUO SEISAKUSHO (1)· patent assignee history
2018Based in Nagoya, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI ULSI SYS CO LTD | 11 | 2000–2008 |
| HITACHI LTD | 6 | 2000–2004 |
| RENESAS TECH CORP | 4 | 2004–2008 |
| KYB CORP | 2 | 2018 |
| CHUO SEISAKUSHO | 1 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hamura, JP | 14 | 2000–2008 |
| Nagoya, JP | 2 | 2018 |
| Saitama, JP | 1 | 1999 |
| Iwatsuki, JP | 1 | 1989 |