Inventor
Wayne Kinney
Inventor
Emmett, ID, US
Overview
Patents· 106 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores29%
H10BElectronic memory devices23%
H10NElectric solid-state devices not otherwise provided for19%
H01LSemiconductor devices13%
H10DInorganic electric semiconductor devices7%
G06FElectric digital data processing2%
H01FMagnets2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
11,063,214Two-terminal reversibly switchable memory device202111,037,942Memory cell and an array of memory cells202110,833,125Memory element with a reactive metal layer202010,803,935Conductive metal oxide structures in non-volatile re-writable memory devices202010,797,106Memory element with a reactive metal layer202010,790,304Integrated assemblies comprising ferroelectric transistors and non-ferroelectric transistors202010,748,594Enabling fast pulse operation202010,726,899Semiconductor structures, memory cells and devices comprising ferroelectric materials, systems including same, and related methods202010,707,298Methods of forming semiconductor structures202010,680,171Two-terminal reversibly switchable memory device202010,636,471Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays202010,585,735Selective reading of memory with improved accuracy202010,586,830Magnetic structures, semiconductor structures, and semiconductor devices202010,553,595Memory cell and an array of memory cells202010,515,996Semiconductor devices with seed and magnetic regions and methods of fabrication201910,431,285Writing to cross-point non-volatile memory201910,340,312Memory element with a reactive metal layer201910,319,426Semiconductor structures, memory cells and devices comprising ferroelectric materials, systems including same, and related methods201910,311,950Conductive metal oxide structures in non-volatile re-writable memory devices201910,224,480Two-terminal reversibly switchable memory device201910,164,168Magnetic memory cell structures, arrays, and semiconductor devices201810,153,026Writing to cross-point non-volatile memory201810,121,824Magnetic structures, semiconductor structures, and semiconductor devices201810,074,662Memory cell and an array of memory cells20189,928,894'Writing to cross-point non-volatile memory'20189,882,016'Transistors, memory cells and semiconductor constructions'20189,876,053Semiconductor devices comprising magnetic memory cells and methods of fabrication20189,871,044'Enhanced charge storage materials, related semiconductor memory cells and semiconductor devices, and related systems and methods'20189,831,425Two-terminal reversibly switchable memory device20179,806,130'Memory element with a reactive metal layer'20179,767,897'Conductive metal oxide structures in non-volatile re-writable memory devices'20179,715,419'Selective reading of memory with improved accuracy'20179,711,565'Semiconductor devices comprising magnetic memory cells'20179,613,676'Writing to cross-point non-volatile memory'20179,590,066'Transistors, memory cells and semiconductor constructions'20179,570,515'Memory element with a reactive metal layer'20179,548,444'Magnetic memory cells and methods of formation'20179,472,560'Memory cell and an array of memory cells'20169,466,787'Memory cells, methods of fabrication, semiconductor device structures, memory systems, and electronic systems'20169,373,775'Methods of forming magnetic memory cells'20169,356,229'Memory cells and methods of fabrication'20169,293,702'Conductive metal oxide structures in non-volatile re-writable memory devices'20169,263,672'Transistors, memory cells and semiconductor constructions'20169,159,408'Memory element with a reactive metal layer'20159,159,913'Two-terminal reversibly switchable memory device'20159,054,030'Memory cells, semiconductor device structures, memory systems, and methods of fabrication'20159,025,364'Selective self-reference read'20159,007,818'Memory cells, semiconductor device structures, systems including such cells, and methods of fabrication'20158,848,425'Conductive metal oxide structures in non volatile re-writable memory devices'20148,796,751'Transistors, memory cells and semiconductor constructions'20148,675,389'Memory element with a reactive metal layer'20148,611,130'Method for fabricating multi-resistive state memory devices'20138,565,006'Conductive metal oxide structures in non volatile re writable memory devices'20138,493,771'Non-volatile memory device ion barrier'20138,395,928'Threshold device for a memory array'20138,358,529'Conductive metal oxide structures in non-volatile re-writable memory devices'20138,320,161'Conductive metal oxide structures in non volatile re writable memory devices'20128,274,817'Non volatile memory device ion barrier'20128,062,942'Method for fabricating multi-resistive state memory devices'20118,045,364'Non-volatile memory device ion barrier'20118,031,510'Ion barrier cap'20118,031,509'Conductive metal oxide structures in non-volatile re-writable memory devices'20117,995,371'Threshold device for a memory array'20117,985,963'Memory using variable tunnel barrier widths'20117,889,539'Multi-resistive state memory device with conductive oxide electrodes'20117,884,349'Selection device for re-writable memory'20117,633,790'Multi-resistive state memory device with conductive oxide electrodes'20097,538,338'Memory using variable tunnel barrier widths'20097,400,006'Conductive memory device with conductive oxide electrodes'20087,394,679'Multi-resistive state element with reactive metal'20087,326,979'Resistive memory device with a treated interface'20087,186,569'Conductive memory stack with sidewall'20077,180,772'High-density NVRAM'20077,095,643'Re-writable memory with multiple memory layers'20067,082,052'Multi-resistive state element with reactive metal'20067,079,442'Layout of driver sets in a cross point memory array'20067,071,008'Multi-resistive state material that uses dopants'20067,067,862'Conductive memory device with conductive oxide electrodes'20067,057,914'Cross point memory array with fast access time'20067,042,035'Memory array with high temperature wiring'20067,038,935'2-terminal trapped charge memory device with voltage switchable multi-level resistance'20066,970,375'Providing a reference voltage to a cross point memory array'20056,965,137'Multi-layer conductive memory device'20056,917,539'High-density NVRAM'20056,909,632'Multiple modes of operation in a cross point array'20056,906,939'Re-writable memory with multiple memory layers'20056,870,755'Re-writable memory with non-linear memory element'20056,850,429'Cross point memory array with memory plugs exhibiting a characteristic hysteresis'20056,834,008'Cross point memory array using multiple modes of operation'20046,831,854'Cross point memory array using distinct voltages'20046,753,561'Cross point memory array using multiple thin films'20045,995,408'Nonvolatile ferroelectric memory with folded bit line architecture'19995,985,714'Method of forming a capacitor'19995,955,758'Method of forming a capacitor plate and a capacitor incorporating same'19995,852,571'Nonvolatile ferroelectric memory with folded bit line architecture'19985,654,222'Method for forming a capacitor with electrically interconnected construction'19975,541,872'Folded bit line ferroelectric memory device'19965,536,672'Fabrication of ferroelectric capacitor and memory cell'19965,424,975'Reference circuit for a non-volatile ferroelectric memory'19955,357,463'Method for reverse programming of a flash EEPROM'19945,345,104'Flash memory cell having antimony drain for reduced drain voltage during programming'19945,179,038'High density trench isolation for MOS circuits'19935,046,043'Ferroelectric capacitor and memory cell including barrier and isolation layers'19914,649,627'Method of fabricating silicon-on-insulator transistors with a shared element'19874,558,508'Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step'19854,532,700'Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer'1985Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1985–1996Based in Albuquerque, NM, US· patent location history
1994–2021Patents assigned to MICRON TECHNOLOGY INC (41)· patent assignee history
1994–2020Based in Boise, ID, US· patent location history
2004–2020Patents assigned to UNITY SEMICONDUCTOR CORP (51)· patent assignee history
2004–2021Based in Emmett, ID, US· patent location history
2011–2014Patents assigned to KINNEY WAYNE (9)· patent assignee history
2012–2013Patents assigned to BREWER JULIE CASPERSON (6)· patent assignee history
2012–2013Patents assigned to SCHLOSS LAWRENCE (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNITY SEMICONDUCTOR CORP | 51 | 2004–2020 |
| MICRON TECHNOLOGY INC | 41 | 1994–2021 |
| KINNEY WAYNEself | 9 | 2011–2014 |
| BREWER JULIE CASPERSON | 6 | 2012–2013 |
| SCHLOSS LAWRENCE | 6 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Emmett, ID, US | 86 | 2004–2021 |
| Boise, ID, US | 14 | 1994–2020 |
| Albuquerque, NM, US | 6 | 1985–1996 |