LexDanaLexDanabeta
Inventor

Tsung-Lin Lee

Inventor
Hsinchu, TW

Overview

88→
Patents
2005–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 88 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices33%
H01LSemiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H10BElectronic memory devices3%
H04LTransmission of digital information, e.g. telegraphic communication1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
Y10TTechnical subjects covered by former us classification1%
B05DProcesses for applying fluent materials to surfaces, in general0%
B08BCleaning in general0%
PatentTitleYear
10,879,240Fin field effect transistor (FinFET) device structure202010,872,893Dual nitride stressor for semiconductor device and method of manufacturing202010,868,142Gate spacer structure and method of forming same202010,861,969Method of forming FinFET structure with reduced Fin buckling202010,811,318FIN field effect transistor (FinFET) device structure with dummy FIN structure202010,727,344Method of manufacturing a semiconductor device with multilayered channel structure202010,720,496FinFET structures and methods of forming the same202010,668,511Method of cleaning process chamber202010,522,409Fin field effect transistor (FinFET) device structure with dummy fin structure and method for forming the same201910,510,887Method for fabricating a strained structure and structure formed201910,483,262Dual nitride stressor for semiconductor device and method of manufacturing201910,395,937Fin patterning for semiconductor devices201910,374,059Structure and formation method of semiconductor device structure with nanowires201910,355,108Method of forming a fin field effect transistor comprising two etching steps to define a fin structure201910,290,550Strain enhancement for FinFETs201910,141,310Short channel effect suppression201810,134,847FinFET structures and methods of forming the same201810,062,782Method of manufacturing a semiconductor device with multilayered channel structure201810,038,080Semiconductor device and manufacturing method thereof20189,997,616Semiconductor device having a strained region20189,953,885STI shape near fin bottom of Si fin in bulk FinFET20189,887,100'Methods of forming semiconductor devices and structures thereof'20189,847,334Structure and formation method of semiconductor device with channel layer20179,761,666'Strained channel field effect transistor'20179,728,461'Method of forming semiconductor device with different threshold voltages'20179,721,829'FinFETs with different fin height and EPI height setting'20179,711,412'FinFETs with different fin heights'20179,659,826'Asymmetric source/drain depths'20179,647,071'FINFET structures and methods of forming the same'20179,640,441'Voids in STI regions for forming bulk FinFETs'20179,601,587'Semiconductor device having elevated structure'20179,577,071'Method of making a strained structure of a semiconductor device'20179,564,529'Method for fabricating a strained structure and structure formed'20179,558,650'Surveillance method, surveillance apparatus, and marking module'20179,515,071'Asymmetric source/drain depths'20169,484,462'Fin structure of fin field effect transistor'20169,425,102'FinFETs with different fin heights'20169,419,134'Strain enhancement for FinFETs'20169,397,097'Gate structure for semiconductor device'20169,385,046'Voids in STI regions for forming bulk FinFETs'20169,349,652'Method of forming semiconductor device with different threshold voltages'20169,331,081'Semiconductor structure and manufacturing method thereof'20169,263,342'Semiconductor device having a strained region'20169,257,344'FinFETs with different fin height and EPI height setting'20169,177,801'FinFET device having a strained region'20159,171,929'Strained structure of semiconductor device and method of making the strained structure'20159,147,594'Method for fabricating a strained structure'20159,112,052'Voids in STI regions for forming bulk FinFETs'20159,087,725'FinFETs with different fin height and EPI height setting'20158,946,828'Semiconductor device having elevated structure and method of manufacturing the same'20158,941,153'FinFETs with different fin heights'20158,878,308'Multi-fin device by self-aligned castle fin formation'20148,847,293'Gate structure for semiconductor device'20148,846,465'Integrated circuit with multi recessed shallow trench isolation'20148,846,466'Forming inter-device STI regions and intra-device STI regions using different dielectric materials'20148,796,156'Cross OD FinFET patterning'20148,748,993'FinFETs with multiple fin heights'20148,747,992'Non-uniform semiconductor device active area pattern formation'20148,723,271'Voids in STI regions for forming bulk FinFETs'20148,673,709'FinFETs with multiple fin heights'20148,653,609'FinFET design with reduced current crowding'20148,653,576'Method of fabricating a SONOS gate structure with dual-thickness oxide'20148,653,608'FinFET design with reduced current crowding'20148,637,135'Non-uniform semiconductor device active area pattern formation'20148,623,718'Tilt implantation for forming FinFETs'20148,610,240'Integrated circuit with multi recessed shallow trench isolation'20138,592,918'Forming inter-device STI regions and intra-device STI regions using different dielectric materials'20138,519,481'Voids in STI regions for forming bulk FinFETs'20138,507,996'Block contact plugs for MOS devices'20138,497,201'Self-assembly pattern for semiconductor integrated circuit'20138,497,528'Method for fabricating a strained structure'20138,445,340'Sacrificial offset protection film for a FinFET device'20138,373,238'FinFETs with multiple Fin heights'20138,338,305'Multi-fin device by self-aligned castle fin formation'20128,174,073'Integrated circuit structures with multiple FinFETs'20128,110,466'Cross OD FinFET patterning'20128,048,795'Self-assembly pattern for semiconductor integrated circuit'20117,847,335'Non-volatile memory device having a generally L-shaped cross-section sidewall SONOS'20107,714,376'Non-volatile memory device with polysilicon spacer and method of forming the same'20107,511,988'Static noise-immune SRAM cells'20097,482,236'Structure and method for a sidewall SONOS memory device'20097,482,231'Manufacturing of memory array and periphery'20097,405,119'Structure and method for a sidewall SONOS memory device'20087,355,236'Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof'20087,292,650'OFDM receiver and metric generator thereof'20077,176,084'Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory'20077,133,479'Frequency synchronization apparatus and method for OFDM systems'20066,868,130'Transmission mode detector for digital receiver'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005Based in Hsin Chu Hsien, TW· patent location history
2006–2020Based in Hsinchu, TW· patent location history
2007–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (47)· patent assignee history
2012–2017Patents assigned to LEE TSUNG-LIN (23)· patent assignee history
2012–2018Patents assigned to YUAN FENG (14)· patent assignee history
2012–2016Patents assigned to CHANG CHANG-YUN (9)· patent assignee history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (37)· patent assignee history
2016–2017Based in New Taipei, TW· patent location history
2020Based in Tainan, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG472007–2016
TAIWAN SEMICONDUCTOR MFG CO LTD372016–2020
LEE TSUNG-LINself232012–2017
YUAN FENG142012–2018
CHANG CHANG-YUN92012–2016
Locations
LocationPatentsSpan
Hsinchu, TW842006–2020
New Taipei, TW22016–2017
Tainan, TW12020
Hsin Chu Hsien, TW12005