Inventor
June Lee
Inventor
Seoul, KR
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores55%
G06FElectric digital data processing23%
G01RMeasuring electric variables7%
H03MCoding7%
A61BDiagnosis1%
A62CFire-fighting1%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light1%
G05FSystems for regulating electric or magnetic variables1%
H04MTelephonic communication1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
10,535,410Hybrid read disturb count management202010,456,052Electronic device having segmental portion on housing thereof201910,347,331Read threshold optimization in flash memories201910,326,473Symbol-based coding for NAND flash devices201910,229,740Memory system of 3D NAND flash and operating method thereof201910,210,041Systems and methods for low latency copy operations in non-volatile memory201910,169,141Modifiable stripe length in flash memory devices201910,157,097Redundant bytes utilization in error correction code201810,148,293Incremental LLR generation for flash memories201810,147,500Hybrid read disturb count management201810,120,585Memory system of optimal read reference voltage and operating method thereof201810,108,472Adaptive read disturb reclaim policy201810,074,439Modeling method of threshold voltage distributions201810,002,073Selective data recycling in non-volatile memory20189,996,412Enhanced chip-kill schemes by using sub-trunk CRC20189,979,417Enhanced chip-kill schemes by using ECC syndrome pattern20189,953,722Methods of system optimization by over-sampling read20189,952,775Unusable column mapping in flash memory devices20189,792,999'Adaptive scheme for incremental step pulse programming of flash memory'20179,733,861'Data temperature profiling by smart counter'20179,653,176'Read disturb reclaim policy'20179,607,710'Read-threshold calibration in a solid state storage system'20179,502,127'System optimization in flash memories'20168,732,425'Electronic apparatus'20147,787,300'Memory devices with page buffer having dual registers and method of using the same'20107,729,176'Program acceleration of a memory device'20107,602,644'Memory devices with page buffer having dual registers and method of using the same'20097,596,026'Program method of non-volatile memory device'20097,539,059'Selective bit line precharging in non volatile memory'20097,227,785'Memory devices with page buffer having dual registers and method of using the same'20077,221,590'Flash memory devices having power level detection circuits'20077,184,307'Flash memory device capable of preventing program disturbance according to partial programming'20077,184,308'Flash memory devices and methods for programming the same'20077,180,811'Semiconductor memory device informing internal voltage level using ready/busy pin'20077,064,986'Non-volatile semiconductor memory device using differential start programming voltage and programming method thereof'20067,042,770'Memory devices with page buffer having dual registers and method of using the same'20066,996,014'Memory devices with page buffer having dual registers and method of using the same'20066,958,935'Nonvolatile semiconductor memory with X8/X16 operation mode using address control'20056,888,756'Low-voltage non-volatile semiconductor memory device'20056,845,041'Non-volatile semiconductor memory device with accelerated column scanning scheme'20056,813,184'NAND flash memory and method of erasing, programming, and copy-back programming thereof'20046,795,366'Internal voltage converter scheme for controlling the power-up slope of internal supply voltage'20046,735,727'Flash memory device with a novel redundancy selection circuit and method of using the same'20046,731,540'Non-volatile semiconductor memory device having shared row selection circuit'20046,724,682'Nonvolatile semiconductor memory device having selective multiple-speed operation mode'20046,567,306'Block architecture option circuit for nonvalatile semiconductor memory devices'20036,377,486'Block architecture option circuit for nonvolatile semiconductor memory devices'20026,018,487'Read-only memory device having bit line discharge circuitry and method of reading data from the same'20005,986,918'Synchronous read only memory device'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2019Patents assigned to SAMSUNG ELECTRONICS CO LTD (25)· patent assignee history
1999–2014Based in Seoul, KR· patent location history
2009–2010Patents assigned to INTEL CORP (2)· patent assignee history
2009–2010Based in San Jose, CA, US· patent location history
2014Patents assigned to LEE JUNE-BUM (1)· patent assignee history
2016–2017Patents assigned to SK HYNIX MEMORY SOLUTIONS INC (4)· patent assignee history
2016–2020Based in Sunnyvale, CA, US· patent location history
2017–2020Patents assigned to SK HYNIX INC (18)· patent assignee history
2019Based in Gyeonggi-do, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 25 | 1999–2019 |
| SK HYNIX INC | 18 | 2017–2020 |
| SK HYNIX MEMORY SOLUTIONS INC | 4 | 2016–2017 |
| INTEL CORP | 2 | 2009–2010 |
| LEE JUNE-BUMself | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seoul, KR | 24 | 1999–2014 |
| Sunnyvale, California, US | 22 | 2016–2020 |
| San Jose, California, US | 2 | 2009–2010 |
| Gyeonggi-do, KR | 1 | 2019 |