LexDanaLexDanabeta
Inventor

Sourav Saha

Inventor
Kolkata, IN

Overview

71→
Patents
2010–2020
Patent span
Physics
Primary field (CPC G)

Patents· 71 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing84%
H04BTransmission4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H01LSemiconductor devices2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
C07DHeterocyclic compounds1%
H03KPulse technique1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
10,534,884Layout of large block synthesis blocks in integrated circuits202010,417,366Layout of large block synthesis blocks in integrated circuits201910,366,191Layout of large block synthesis blocks in integrated circuits201910,242,140Layout of large block synthesis blocks in integrated circuits201910,235,487Layout of large block synthesis blocks in integrated circuits201910,229,238Congestion aware layer promotion201910,223,489Placement clustering-based white space reservation201910,223,491Integrated circuit design changes using through-silicon vias201910,169,519Area sharing between multiple large block synthesis (LBS) blocks201910,169,523Timing constraints formulation for highly replicated design modules201910,140,414Critical region identification201810,120,970Global routing framework of integrated circuit based on localized routing optimization20189,946,830Area sharing between multiple large block synthesis (LBS) blocks20189,928,329'Layout of large block synthesis blocks in integrated circuits'20189,910,948'Layout of large block synthesis blocks in integrated circuits'20189,858,377'Constraint-driven pin optimization for hierarchical design convergence'20189,798,847'Cross-hierarchy interconnect adjustment for power recovery'20179,734,270'Control path power adjustment for chip design'20179,734,268'Slack redistribution for additional power recovery'20179,715,565'Physical aware technology mapping in synthesis'20179,715,572'Hierarchical wire-pin co-optimization'20179,710,585'Physical aware technology mapping in synthesis'20179,703,910'Control path power adjustment for chip design'20179,703,923'Timing constraints formulation for highly replicated design modules'20179,703,920'Intra-run design decision process for circuit synthesis'20179,703,924'Timing constraints formulation for highly replicated design modules'20179,697,322'Hierarchical wire-pin co-optimization'20179,690,900'Intra-run design decision process for circuit synthesis'20179,684,757'Cross-hierarchy interconnect adjustment for power recovery'20179,684,759'De-coupling capacitance placement'20179,684,751'Slack redistribution for additional power recovery'20179,679,101'Circuit placement with electro-migration mitigation'20179,679,099'De-coupling capacitance placement'20179,672,322'Virtual positive slack in physical synthesis'20179,672,321'Virtual positive slack in physical synthesis'20179,672,314'Logic structure aware circuit routing'20179,659,135'Logic structure aware circuit routing'20179,659,140'Critical region identification'20179,633,928'Through-silicon via access device for integrated circuits'20179,576,102'Timing constraints formulation for highly replicated design modules'20179,569,580'Integrated circuit design changes using through-silicon vias'20179,569,581'Logic structure aware circuit routing'20179,563,736'Placement aware functional engineering change order extraction'20179,552,451'Cross-hierarchy interconnect adjustment for power recovery'20179,542,327'Selective mirroring in caches for logical volumes'20179,536,037'Circuit placement with electro-migration mitigation'20179,514,265'Congestion aware layer promotion'20169,501,603'Integrated circuit design changes using through-silicon vias'20169,495,502'Congestion aware layer promotion'20169,483,601'Circuit routing based on total negative slack'20169,471,735'Boundary based power guidance for physical synthesis'20169,471,741'Circuit routing based on total negative slack'20169,443,048'Physical aware technology mapping in synthesis'20169,443,047'Physical aware technology mapping in synthesis'20169,443,049'Boundary based power guidance for physical synthesis'20169,418,190'Virtual sub-net based routing'20169,412,682'Through-silicon via access device for integrated circuits'20169,384,316'Path-based congestion reduction in integrated circuit routing'20169,378,326'Critical region identification'20169,378,151'System and method of hinted cache data removal'20169,286,428'Boundary based power guidance for physical synthesis'20169,245,084'Virtual sub-net based routing'20169,245,074'Boundary based power guidance for physical synthesis'20169,092,587'Congestion estimation techniques at pre-synthesis stage'20159,053,285'Thermally aware pin assignment and device placement'20159,009,642'Congestion estimation techniques at pre-synthesis stage'20158,966,422'Median line based critical timing path optimization'20158,930,873'Creating regional routing blockages in integrated circuit design'20158,826,208'Computational thermal analysis during microchip design'20148,541,240'Colorimetric and fluorimetric fluoride sensing'20137,710,295'Inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2020Based in Kolkata, IN· patent location history
2013Patents assigned to GUHA SAMIT (1)· patent assignee history
2013Based in Tallahassee, FL, US· patent location history
2014–2020Patents assigned to IBM (67)· patent assignee history
2014–2017Based in Barrackpur, IN· patent location history
2016–2017Patents assigned to AVAGO TECHNOLOGIES GENERAL IP (2)· patent assignee history
2016–2017Patents assigned to LSI CORP (2)· patent assignee history
2016–2017Based in Bangalore, IN· patent location history
2017Based in Kolkarta, IN· patent location history
2018Patents assigned to INT BUISINESS MACHINES CORPORATOIN (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM672014–2020
AVAGO TECHNOLOGIES GENERAL IP22016–2017
LSI CORP22016–2017
GUHA SAMIT12013
INT BUISINESS MACHINES CORPORATOIN12018
Locations
LocationPatentsSpan
Kolkata, IN622010–2020
Barrackpur, IN52014–2017
Bangalore, IN22016–2017
Kolkarta, IN12017
Tallahassee, Florida, US12013