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Inventor

Fabiano Fontana

Inventor
San Jose, CA, US

Overview

31→
Patents
1995–2015
Patent span
Electricity
Primary field (CPC H)

Patents· 31 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique54%
G11CStatic stores37%
G06FElectric digital data processing6%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
PatentTitleYear
8,971,146'Dual-port SRAM with bit line clamping'20158,553,463'Voltage discharge circuit having divided discharge current'20138,451,679'Dual-port SRAM with bit line clamping'20138,351,287'Bitline floating circuit for memory power reduction'20137,957,208'Flexible memory architectures for programmable logic devices'20117,724,029'Power management for integrated circuits such as programmable logic devices'20107,702,977'Programmable logic devices with custom identification systems and methods'20107,560,953'Power management systems and methods for programmable logic devices'20097,554,358'Programmable logic devices with user non-volatile memory'20097,546,498'Programmable logic devices with custom identification systems and methods'20097,495,970'Flexible memory architectures for programmable logic devices'20097,459,931'Programmable logic devices with transparent field reconfiguration'20087,378,873'Programmable logic device providing a serial peripheral interface'2008RE040311'Zero-power programmable memory cell'20087,313,025'Flash memory erase verification systems and methods'20077,187,586'Flash memory erase verification systems and methods'20076,838,904'Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation'20056,650,142'Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use'20036,611,463'Zero-power programmable memory cell'20036,489,806'Zero-power logic cell for use in programmable logic devices'20026,133,769'Phase locked loop with a lock detector'20005,982,683'Enhanced method of testing semiconductor devices having nonvolatile elements'19995,748,525'Array cell circuit with split read/write line'19985,668,488'Input buffer for a high density programmable logic device'19975,568,066'Sense amplifier and or gate for a high density programmable logic device'19965,495,195'Output buffer for a high density programmable logic device'19965,442,304'CMOS logic gate clamping circuit'19955,438,278'High speed CMOS output buffer circuit minimizes propagation delay and crowbar current'19955,432,463'High speed NOR gate with small output voltage swings'19955,418,482'High-speed sense amplifier with regulated feedback'19955,402,081'Input buffer circuit with improved speed performance'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–1999Patents assigned to ADVANCED MICRO DEVICES INC (10)· patent assignee history
1995–1998Based in Santa Clara, CA, US· patent location history
1999–2015Based in San Jose, CA, US· patent location history
2002–2015Patents assigned to LATTICE SEMICONDUCTOR CORP (20)· patent assignee history
2013Patents assigned to FONTANA FABIANO (3)· patent assignee history
2013Patents assigned to CHEN ZHENG (1)· patent assignee history
2013Patents assigned to MCLAURY LOREN (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LATTICE SEMICONDUCTOR CORP202002–2015
ADVANCED MICRO DEVICES INC101995–1999
FONTANA FABIANOself32013
CHEN ZHENG12013
MCLAURY LOREN12013
Locations
LocationPatentsSpan
San Jose, California, US221999–2015
Santa Clara, California, US91995–1998