Inventor

ALEXANDER REZNICEK

Inventor

US

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 242 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices26%

H10DInorganic electric semiconductor devices23%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

H10BElectronic memory devices9%

B82YSpecific uses or applications of nanostructures8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%

H10NElectric solid-state devices not otherwise provided for7%

G11CStatic stores4%

G06NComputing arrangements based on specific computational models1%

G06FElectric digital data processing1%

PatentTitleYear

12,588,216Pillar based memory (MRAM) embedded within the buried power rail within a backside power distribution network2026 12,588,217Programming current control for artificial intelligence (AI) devices2026 12,575,332CoFeB based magnetic tunnel junction device with boron encapsulation layer2026 12,575,330Ordered alloy magnetic tunnel junction with simplified seed structure2026 12,568,650Profile engineering for deep trenches in a semiconductor device2026 12,556,804Policy for preventing unauthorized photo capture2026 12,557,320FVBP without backside Si recess2026 12,550,625MRAM with doped silicon-germanium-tin alloy electrodes2026 12,550,705Self-aligned backside gate contact2026 12,550,371Separate gate complementary field-effect transistor2026 12,550,620Top electrode to metal line connection for magneto-resistive random-access memory stack height reduction2026 12,535,796Embedded sensor chips in 3D and 4D printed structures through selective filament infusion2026 12,538,786Backside contact for semiconductor device2026 12,490,501Vertically stacked cascode bipolar junction transistor (BJT) pair sensor2025 12,490,511Stacked complementary field effect transistors2025 12,482,750Power distribution network with backside power rail2025 12,484,262Tunnel field effect transistor devices2025 12,484,297Forksheet transistor with dual depth late cell boundary cut2025 12,471,364Hybrid stacked field effect transistors2025 12,464,796Gate induced drain leakage reduction in FinFETs2025 12,464,957Textured cobalt aluminum/magnesium-aluminum-oxide pedestal for memory devices2025 12,457,780Semiconductor device with void under source/drain region for backside contact2025 12,453,146Epi growth uniformity with source/drain placeholder2025 12,439,633VTFET with controlled fin height2025 12,432,968Nanowire source/drain formation for nanosheet device2025 12,408,369Vertical transport field effect transistors having different threshold voltages along the channel2025 12,402,544Antenna assisted ReRAM formation2025 12,402,342Nanosheet device with T-shaped dual inner spacer2025 12,382,682Gate-all-around nanosheet-FET with variable channel geometries for performance optimization2025 12,364,174Global heater for phase change memory2025 12,364,164Reactive serial resistance reduction for magnetoresistive random-access memory devices2025 12,329,045Phase change memory programming current leakage reduction2025 12,324,237Diffusion-break region in stacked-FET integrated circuit device2025 12,317,537Reduced parasitic capacitance semiconductor device containing at least one local interconnect passthrough structure2025 12,317,764Uniform voltage drop in arrays of memory devices2025 12,310,263Phase change memory gaps2025 12,293,469Virtual reality design navigation using a temporal collaboration dependency map2025 12,268,016Buried power rail formation for vertical field effect transistors2025 12,262,552Source/drain epitaxy process in stacked FET2025 12,255,106Multi-Vt nanosheet devices2025 12,245,530Phase change memory with concentric ring-shaped heater2025 12,236,539Contextual positioning in virtual space2025 12,237,328Minimizing shorting between FinFET epitaxial regions2025 12,230,676Nanosheet device with tri-layer bottom dielectric isolation2025 12,225,835Resistive switching device having a protective electrode ring2025 12,219,884Phase change memory with conductive rings2025 12,191,352Using different work-functions to reduce gate-induced drain leakage current in stacked nanosheet transistors2025 12,183,826Vertical field effect transistor with low-resistance bottom source-drain contact2024 12,176,434Strained semiconductor FET devices with epitaxial quality improvement2024 12,154,985Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices2024 12,154,899Darlington pair bipolar junction transistor sensor2024 12,156,395Metal gate patterning for logic and SRAM in nanosheet devices2024 12,155,967Contextual positioning in virtual space2024 12,144,270Back end of line embedded RRAM structure with grain growth enhancement2024 12,144,271Back end of line embedded RRAM structure with low forming voltage2024 12,142,526Stacked device with buried interconnect2024 12,136,671Gate-all-around field-effect transistor having source side lateral end portion smaller than a thickness of channel portion and drain side lateral end portion2024 12,127,482Multi-state SOT-MRAM structure2024 12,118,662Optimizing computer-based generation of three-dimensional virtual objects2024 12,108,686Paramagnetic hexagonal metal phase coupling spacer2024 12,100,744Wrap around contact process margin improvement with early contact cut2024 12,100,653Resistance tunable fuse structure formed by embedded thin metal layers2024 12,100,766Integrated short channel omega gate FinFET and long channel FinFET2024 12,080,714Buried local interconnect between complementary field-effect transistor cells2024 12,080,640Self-aligned via to metal line for interconnect2024 12,075,627AI accelerator with MRAM, PCM, and recessed PCM bottom electrode2024 12,026,605FeFET unit cells for neuromorphic computing2024 12,016,251Spin-orbit torque and spin-transfer torque magnetoresistive random-access memory stack2024 12,009,395Self-aligned block for vertical FETs2024 12,009,435Integrated nanosheet field effect transistors and floating gate memory cells2024 12,009,422Self aligned top contact for vertical transistor2024 11,990,412Buried power rails located in a base layer including first, second, and third etch stop layers2024 RE049954Fabrication of nano-sheet transistors with different threshold voltages2024 11,957,069Contact resistance of a metal liner in a phase change memory cell2024 11,942,388Temperature-assisted device with integrated thin-film heater2024 11,929,404Transistor gates having embedded metal-insulator-metal capacitors2024 11,915,734Spin-orbit-torque magnetoresistive random-access memory with integrated diode2024 11,910,734Phase change memory cell with ovonic threshold switch2024 11,901,449Series connected stacked vertical transistors for high voltage applications2024 11,894,444Secure chip identification using random threshold voltage variation in a field effect transistor structure as a physically unclonable function2024 11,894,433Method and structure to improve stacked FET bottom EPI contact2024 11,887,890Partial self-aligned contact for MOL2024 11,881,505Tri-layer STI liner for nanosheet leakage control2024 11,869,983Low voltage/power junction FET with all-around junction gate2024 11,869,893Stacked field effect transistor with wrap-around contacts2024 11,869,812Stacked complementary field effect transistors2024 11,862,710Vertical transistor including symmetrical source/drain extension junctions2024 11,855,180Gate induced drain leakage reduction in FinFETs2023 11,855,148Vertical field effect transistor with dual threshold voltage2023 11,848,264Semiconductor structure with stacked vias having dome-shaped tips2023 11,830,877Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages2023 11,817,497Vertical field effect transistor inverter with single fin device2023 11,818,886Low program voltage flash memory cells with embedded heater in the control gate2023 11,798,867Half buried nFET/pFET epitaxy source/drain strap2023 11,800,698Semiconductor structure with embedded capacitor2023 11,791,290Physical unclonable function for secure integrated hardware systems2023 11,756,996Formation of wrap-around-contact for gate-all-around nanosheet FET2023 11,757,036Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices2023 11,742,246Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors2023 11,742,425FinFET device with partial interface dipole formation for reduction of gate induced drain leakage2023 11,742,354Top epitaxial layer and contact for VTFET2023 11,735,480Transistor having source or drain formation assistance regions with improved bottom isolation2023 11,737,379Antenna assisted ReRAM formation2023 11,735,628Nanosheet metal-oxide semiconductor field effect transistor with asymmetric threshold voltage2023 11,737,289High density ReRAM integration with interconnect2023 11,715,794VTFET with cell height constraints2023 11,711,982Laser anneal for MRAM encapsulation enhancement2023 11,711,989Phase change memory2023 11,697,889Three-dimensionally stretchable single crystalline semiconductor membrane2023 11,695,004Vertical bipolar junction transistor and vertical field effect transistor with shared floating region2023 11,688,646Reduced source/drain coupling for CFET2023 11,683,941Resistive random access memory integrated with vertical transport field effect transistors2023 11,682,718Vertical bipolar junction transistor with all-around extrinsic base and epitaxially graded intrinsic base2023 11,676,894Resistance tunable fuse structure formed by embedded thin metal layers2023 11,665,983Phase change memory cell with ovonic threshold switch2023 11,664,271Dual damascene with short liner2023 11,664,375Minimizing shorting between FinFET epitaxial regions2023 11,664,455Wrap-around bottom contact for bottom source/drain2023 11,659,780Phase change memory structure with efficient heating system2023 11,646,372Vertical transistor floating body one transistor DRAM memory cell2023 11,646,362Vertical transport field-effect transistor structure having increased effective width and self-aligned anchor for source/drain region formation2023 11,631,462Temperature assisted programming of flash memory for neuromorphic computing2023 11,621,332Wraparound contact to a buried power rail2023 11,621,297Stackable symmetrical operation memory bit cell structure with bidirectional selectors2023 11,605,673Dual resistive random-access memory with two transistors2023 11,594,617Vertical reconfigurable field effect transistor2023 11,587,837Oxygen vacancy passivation in high-k dielectrics for vertical transport field effect transistor2023 11,588,103Resistive memory array2023 11,575,025Vertical field effect transistor with self-aligned source and drain top junction2023 11,575,023Secure chip identification using random threshold voltage variation in a field effect transistor structure as a physically unclonable function2023 11,575,028Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices2023 11,569,438Magnetoresistive random-access memory device2023 11,563,082Reduction of drain leakage in nanosheet device2023 11,557,675Reduction of bottom epitaxy parasitics for vertical transport field effect transistors2023 11,557,651Nanosheet transistors with inner airgaps2023 11,557,663Twin gate tunnel field-effect transistor (FET)2023 11,551,750Enhanced state dual memory cell2023 11,552,243MRAM structure with ternary weight storage2023 11,527,616Vertical transport CMOS transistors with asymmetric threshold voltage2022 11,527,574Stacked resistive memory with individual switch control2022 11,521,927Buried power rail for scaled vertical transport field effect transistor2022 11,515,430Tilted nanowire transistor2022 11,500,614Stacked FET multiply and accumulate integrated circuit2022 11,502,169Nanosheet semiconductor devices with n/p boundary structure2022 11,495,668Full air-gap spacers for gate-all-around nanosheet field effect transistors2022 11,495,669Full air-gap spacers for gate-all-around nanosheet field effect transistors2022 11,489,045Nanosheet transistor with body contact2022 11,476,264Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices2022 11,456,308Low-voltage flash memory integrated with a vertical field effect transistor2022 11,450,659On-chip decoupling capacitor2022 11,444,165Asymmetric threshold voltages in semiconductor devices2022 11,444,185III-V lateral bipolar junction transistor on local facetted buried oxide layer2022 11,437,502III-V lateral bipolar junction transistor on local facetted buried oxide layer2022 11,430,660Confined work function material for gate-all around transistor devices2022 11,430,514Setting an upper bound on RRAM resistance2022 11,424,361Stacked vertical tunnel FET methods2022 11,424,403Magnetoresistive random-access memory cell having a metal line connection2022 11,411,049Symmetric read operation resistive random-access memory cell with bipolar junction selector2022 11,411,048Magnetoresistive random-access memory device structure2022 11,404,581Wimpy vertical transport field effect transistor with dipole liners2022 11,398,480Transistor having forked nanosheets with wraparound contacts2022 11,387,342Multi threshold voltage for nanosheet2022 11,380,641Pillar bump with noble metal seed layer for advanced heterogeneous integration2022 11,374,167Reducing parasitic bottom electrode resistance of embedded MRAM2022 11,362,194Transistor having confined source/drain regions with wrap-around source/drain contacts2022 11,362,086Diode connected vertical transistor2022 11,355,633Vertical field effect transistor with bottom source-drain region2022 11,355,553Resistive random access memory integrated under a vertical field effect transistor2022 11,349,029Structure to enable titanium contact liner on pFET source/drain regions2022 11,348,999Nanosheet semiconductor devices with sigma shaped inner spacer2022 11,335,804Scalable vertical transistor bottom source-drain epitaxy2022 11,329,167Fishbone long channel nanosheet device2022 11,329,142Vertical transistor with body contact2022 11,322,359Single process for liner and metal fill2022 11,315,938Stacked nanosheet rom2022 11,315,923Stacked nanosheet inverter2022 11,309,216Large grain copper interconnect lines for MRAM2022 11,302,794FinFET with dual work function metal2022 11,302,813Wrap around contact for nanosheet source drain epitaxy2022 11,295,983Transistor having source or drain formation assistance regions with improved bottom isolation2022 11,295,988Semiconductor FET device with bottom isolation and high-k first2022 11,289,484Forming source and drain regions for sheet transistors2022 11,282,947Heterojunction bipolar transistor with a silicon oxide layer on a silicon germanium base2022 11,276,576Gate metal patterning to avoid gate stack attack due to excessive wet etching2022 11,271,108Low-noise gate-all-around junction field effect transistor2022 11,271,107Reduction of bottom epitaxy parasitics for vertical transport field effect transistors2022 11,270,910Interconnect structure with partial sidewall liner2022 11,251,301Cross-bar vertical transport field effect transistors without corner rounding2022 11,251,185Stacked complementary junction FETs for analog electronic circuits2022 11,251,094Oxygen vacancy passivation in high-k dielectrics for vertical transport field effect transistor2022 11,251,304Wrap-around bottom contact for bottom source/drain2022 11,244,864Reducing parasitic capacitance within semiconductor devices2022 11,245,009Asymmetric channel FinFETs with wrap around channel2022 11,245,025Gate last vertical transport field effect transistor2022 11,239,115Partial self-aligned contact for MOL2022 11,239,343Vertical transistor including symmetrical source/drain extension junctions2022 11,239,359Fabricating a gate-all-around (GAA) field effect transistor having threshold voltage asymmetry by thinning source side lateral end portion of the nanosheet layer2022 11,239,414Physical unclonable function for MRAM structures2022 11,233,137Transistors and methods of forming transistors using vertical nanowires2022 11,227,923Wrap around contact process margin improvement with early contact cut2022 11,226,252Multilayered magnetic free layer structure in magnetic tunnel junction arrays for sub-micrometer resolution pressure sensors2022 11,227,922Sloped epitaxy buried contact2022 11,222,979Field-effect transistor devices with sidewall implant under bottom dielectric isolation2022 11,222,922Resistive random access memory cells integrated with shared-gate vertical field effect transistors2022 11,205,698Multiple work function nanosheet transistors with inner spacer modulation2021 11,205,728Vertical field effect transistor with reduced parasitic capacitance2021 11,201,242Structure to enable titanium contact liner on pFET source/drain regions2021 11,201,092Gate channel length control in VFET2021 11,201,153Stacked field effect transistor with wrap-around contacts2021 11,201,241Vertical field effect transistor and method of manufacturing a vertical field effect transistor2021 11,196,000Low forming voltage non-volatile memory (NVM)2021 11,189,725VTFET with cell height constraints2021 11,189,712Formation of vertical transport field-effect transistor structure having increased effective width2021 11,187,672Superhydrophobic electrode and biosensing device using the same2021 11,189,661FinFET 2T2R RRAM2021 11,189,701Bipolar junction transistor with vertically integrated resistor2021 11,183,632Self-aligned edge passivation for robust resistive random access memory connection2021 11,183,558Nanosheet transistor having partially self-limiting bottom isolation extending into the substrate and under the source/drain and gate regions2021 11,177,225Semiconductor device including physical unclonable function2021 11,177,372Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices2021 11,177,370Vertical field effect transistor with self-aligned source and drain top junction2021 11,177,258Stacked nanosheet CFET with gate all around structure2021 11,177,366Gate induced drain leakage reduction in FinFETs2021 11,165,017Replacement bottom electrode structure process to form misalignment tolerate MRAM with high yield2021 11,164,792Complementary field-effect transistors2021 11,164,960Transistor having in-situ doped nanosheets with gradient doped channel regions2021 11,164,782Self-aligned gate contact compatible cross couple contact formation2021 11,164,907Resistive random access memory integrated with stacked vertical transistors2021 11,164,793Reduced source/drain coupling for CFET2021 11,164,787Two-stage top source drain epitaxy formation for vertical field effect transistors enabling gate last formation2021 11,158,715Vertical FET with asymmetric threshold voltage and channel thicknesses2021 11,158,756FinFET radiation dosimeter2021 11,158,636Nanosheet device integrated with a FINFET transistor2021 11,158,729Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices2021 11,158,538Interconnect structures with cobalt-infused ruthenium liner and a cobalt cap2021 11,152,264Multi-Vt scheme with same dipole thickness for gate-all-around transistors2021 11,152,265Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors2021 11,152,478Vertical transistors with buried metal silicide bottom contact2021 11,152,510Long channel optimization for gate-all-around transistors2021 11,145,668EEPROM cell and array having stacked nanosheet field effect transistors with a common floating gate2021 11,145,380Analog nonvolatile memory cells using dopant activation2021 11,145,816Resistive random access memory cells integrated with vertical field effect transistor2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to IBM (236)· patent assignee history

2021–2026Based in US· patent location history

2022Patents assigned to ELPIS TECH INC (1)· patent assignee history

2022Patents assigned to GLOBALFOUNDRIES US INC (1)· patent assignee history

2023–2024Patents assigned to TESSERA LLC (2)· patent assignee history

2025Patents assigned to ADEIA SEMICONDUCTOR SOLUTIONS LLC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	236	2021–2026
TESSERA LLC	2	2023–2024
ADEIA SEMICONDUCTOR SOLUTIONS LLC	1	2025
ELPIS TECH INC	1	2022
GLOBALFOUNDRIES US INC	1	2022

Locations

Location	Patents	Span
US	242	2021–2026