Inventor

Ricky C. Hetherington

Inventor

Pleasanton, CA, US

Overview

60→

Patents

1989–2015

Patent span

Physics

Primary field (CPC G)

Patents· 60 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing91%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%

G11CStatic stores2%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%

PatentTitleYear

9,208,084'Extended main memory hierarchy having flash memory for page fault handling'2015 8,180,981'Cache coherent support for flash in a memory hierarchy'2012 7,873,776'Multiple-core processor with support for multiple virtual processors'2011 7,716,521'Multiple-core, multithreaded processor with flexible error steering mechanism'2010 7,685,354'Multiple-core processor with flexible mapping of processor cores to cache banks'2010 7,644,221'System interface unit'2010 7,587,658'ECC encoding for uncorrectable errors'2009 7,529,894'Use of FBDIMM channel as memory channel and coherence channel'2009 7,487,327'Processor and method for device-specific memory address translation'2009 7,401,206'Apparatus and method for fine-grained multithreading in a multipipelined processor core'2008 7,398,360'Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors'2008 7,370,243'Precise error handling in a fine grain multithreaded multicore processor'2008 7,353,340'Multiple independent coherence planes for maintaining coherency'2008 7,330,988'Method and apparatus for power throttling in a multi-thread processor'2008 7,240,160'Multiple-core processor with flexible cache directory scheme'2007 6,684,299'Method for operating a non-blocking hierarchical cache throttle'2004 6,484,240'Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols'2002 6,430,654'Apparatus and method for distributed non-blocking multi-level cache'2002 6,360,285'Apparatus for determining memory bank availability in a computer system'2002 6,353,877'Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write'2002 6,327,667'Apparatus and method for operating clock sensitive devices in multiple timing domains'2001 6,269,426'Method for operating a non-blocking hierarchical cache throttle'2001 6,240,502'Apparatus for dynamically reconfiguring a processor'2001 6,219,723'Method and apparatus for moderating current demand in an integrated circuit processor'2001 6,212,602'Cache tag caching'2001 6,154,812'Method for inhibiting thrashing in a multi-level non-blocking cache system'2000 6,154,815'Non-blocking hierarchical cache throttle'2000 6,148,371'Multi-level non-blocking cache system with inhibiting thrashing'2000 6,145,054'Apparatus and method for handling multiple mergeable misses in a non-blocking cache'2000 6,128,711'Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes'2000 6,122,709'Cache with reduced tag information storage'2000 6,119,205'Speculative cache line write backs to avoid hotspots'2000 6,081,873'In-line bank conflict detection and resolution in a multi-ported non-blocking cache'2000 6,076,129'Distributed data bus sequencing for a system bus with separate address and data bus protocols'2000 6,073,212'Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags'2000 6,058,472'Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine'2000 6,052,775'Method for non-intrusive cache fills and handling of load misses'2000 6,006,326'Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies'1999 5,999,727'Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions'1999 5,996,048'Inclusion vector architecture for a level two cache'1999 5,987,594'Apparatus for executing coded dependent instructions having variable latencies'1999 5,978,864'Method for thermal overload detection and prevention for an intergrated circuit processor'1999 5,948,106'System for thermal overload detection and prevention for an integrated circuit processor'1999 5,930,819'Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache'1999 5,909,697'Reducing cache misses by snarfing writebacks in non-inclusive memory systems'1999 5,890,008'Method for dynamically reconfiguring a processor'1999 5,666,551'Distributed data bus sequencing for a system bus with separate address and data bus protocols'1997 5,475,690'Delay compensated signal propagation'1995 5,349,651'System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation'1994 5,285,323'Integrated circuit chip having primary and secondary random access memories for a hierarchical cache'1994 5,222,224'Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system'1993 5,222,223'Method and apparatus for ordering and queueing multiple memory requests'1993 5,142,631'System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register'1992 5,125,083'Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system'1992 5,113,515'Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer'1992 5,019,965'Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width'1991 4,995,041'Write back buffer with error correcting capabilities'1991 4,985,825'System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer'1991 4,982,402'Method and apparatus for detecting and correcting errors in a pipelined computer system'1991 4,888,679'Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–2000Patents assigned to DIGITAL EQUIPMENT CORP (15)· patent assignee history

1989–1994Based in Northboro, MA, US· patent location history

1994Based in Northborough, MA, US· patent location history

1995–2002Based in Westboro, MA, US· patent location history

1999–2010Patents assigned to SUN MICROSYSTEMS INC (37)· patent assignee history

1999–2015Based in Pleasanton, CA, US· patent location history

2000–2002Patents assigned to COMPAQ COMPUTER CORP (4)· patent assignee history

2001Based in Westborough, MA, US· patent location history

2010–2015Patents assigned to ORACLE AMERICA INC (4)· patent assignee history

2012–2015Patents assigned to HETHERINGTON RICKY C (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SUN MICROSYSTEMS INC	37	1999–2010
DIGITAL EQUIPMENT CORP	15	1989–2000
COMPAQ COMPUTER CORP	4	2000–2002
ORACLE AMERICA INC	4	2010–2015
HETHERINGTON RICKY Cself	2	2012–2015

Locations

Location	Patents	Span
Pleasanton, California, US	41	1999–2015
Northboro, Massachusetts, US	11	1989–1994
Westboro, Massachusetts, US	6	1995–2002
Westborough, Massachusetts, US	1	2001
Northborough, Massachusetts, US	1	1994