Inventor

Paul Kwok Keung Ho

Inventor

Singapore, SG

Overview

33→

Patents

2000–2019

Patent span

Electricity

Primary field (CPC H)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%

B08BCleaning in general4%

C11DDetergent compositions4%

C23CCoating metallic material4%

C23FNon-mechanical removal of metallic material from surface4%

C23GCleaning or de-greasing of metallic material by chemical methods other than electrolysis4%

C25DProcesses for the electrolytic or electrophoretic production of coatings4%

H01LSemiconductor devices4%

PatentTitleYear

10,290,432Method for forming perovskite solar cell with printable carbon electrode2019 9,583,711'Conductive and photosensitive polymers'2017 9,243,340'Non-vacuum method of manufacturing light-absorbing materials for solar cell application'2016 7,452,808'Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding'2008 7,060,613'Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding'2006 6,987,321'Copper diffusion deterrent interface'2006 6,967,162'Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding'2005 6,813,796'Apparatus and methods to clean copper contamination on wafer edge'2004 6,720,204'Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding'2004 6,692,579'Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence'2004 6,683,002'Method to create a copper diffusion deterrent interface'2004 6,565,664'Method for stripping copper in damascene interconnects'2003 6,548,413'Method to reduce microloading in metal etching'2003 6,540,841'Method and apparatus for removing contaminants from the perimeter of a semiconductor substrate'2003 6,475,810'Method of manufacturing embedded organic stop layer for dual damascene patterning'2002 6,429,117'Method to create copper traps by modifying treatment on the dielectrics surface'2002 6,394,114'Method for stripping copper in damascene interconnects'2002 6,391,783'Method to thin down copper barriers in deep submicron geometries by using alkaline earth element, barrier additives, or self assembly technique'2002 6,368,958'Method to deposit a cooper seed layer for dual damascence interconnects'2002 6,365,508'Process without post-etch cleaning-converting polymer and by-products into an inert layer'2002 6,358,821'Method of copper transport prevention by a sputtered gettering layer on backside of wafer'2002 6,350,689'Method to remove copper contamination by using downstream oxygen and chelating agent plasma'2002 6,340,608'Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads'2002 6,309,982'Method for minimizing copper diffusion by doping an inorganic dielectric layer with a reducing agent'2001 6,274,499'Method to avoid copper contamination during copper etching and CMP'2001 6,261,955'Application of vapor phase HFACAC-based compound for use in copper decontamination and cleaning processes'2001 6,261,954'Method to deposit a copper layer'2001 6,255,266'Alkyldione peroxides as cleaning solutions for wafer fabs'2001 6,251,786'Method to create a copper dual damascene structure with less dishing and erosion'2001 6,225,221'Method to deposit a copper seed layer for dual damascene interconnects'2001 6,184,138'Method to create a controllable and reproducible dual copper damascene structure'2001 6,132,521'Cleaning metal surfaces with alkyldione peroxides'2000 6,017,826'Chlorine containing plasma etch method with enhanced sidewall passivation and attenuated microloading effect'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2008Patents assigned to CHARTERED SEMICONDUCTOR MFG (30)· patent assignee history

2000–2008Based in Singapore, SG· patent location history

2006Based in Cainese, SG· patent location history

2016–2019Patents assigned to NANO & ADVANCED MATERIALS INST LTD (3)· patent assignee history

2016Based in HK, HK· patent location history

2017–2019Based in Hong Kong, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
CHARTERED SEMICONDUCTOR MFG	30	2000–2008
NANO & ADVANCED MATERIALS INST LTD	3	2016–2019

Locations

Location	Patents	Span
Singapore, SG	29	2000–2008
Hong Kong, CN	2	2017–2019
HK, HK	1	2016
Cainese, SG	1	2006