Inventor

Albert Hartono

Inventor
Santa Clara, CA, US

Overview

17→
Patents
2015–2019
Patent span
Physics
Primary field (CPC G)

Patents· 17 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
10,402,177Methods and systems to vectorize scalar computer program loops having loop-carried dependences201910,372,450Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate201910,324,768Lightweight restricted transactional memory for speculative compiler optimization20199,921,832'Instruction to reduce elements in a vector register with strided access pattern'20189,910,650'Method and apparatus for approximating detection of overlaps between memory ranges'20189,898,266'Loop vectorization methods and apparatus'20189,798,541'Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register'20179,733,913'Methods and systems to vectorize scalar computer program loops having loop-carried dependences'20179,720,667'Automatic loop vectorization using hardware transactional memory'20179,710,279'Method and apparatus for speculative vectorization'20179,703,558'Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate'20179,690,582'Instruction and logic for cache-based speculative vectorization'20179,588,814'Fast approximate conflict detection'20179,268,626'Apparatus and method for vectorization with speculation support'20169,268,541'Methods and systems to vectorize scalar computer program loops having loop-carried dependences'20169,244,677'Loop vectorization methods and apparatus'20169,189,236'Speculative non-faulting loads and gathers'2015

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2015–2019Patents assigned to INTEL CORP (17)· patent assignee history
2015–2017Patents assigned to HARTONO ALBERT (5)· patent assignee history
2015–2017Patents assigned to VASUDEVAN NALINI (5)· patent assignee history
2015–2017Patents assigned to BHARADWAJ JAYASHANKAR (4)· patent assignee history
2015–2017Patents assigned to LEE VICTOR W (4)· patent assignee history
2015–2019Based in Santa Clara, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP172015–2019
HARTONO ALBERTself52015–2017
VASUDEVAN NALINI52015–2017
BHARADWAJ JAYASHANKAR42015–2017
LEE VICTOR W42015–2017
Locations
LocationPatentsSpan
Santa Clara, California, US172015–2019