Inventor

Per Hammarlund

Inventor

Hillsboro, OR, US

Overview

2000–2020

Patent span

Physics

Primary field (CPC G)

Patents· 90 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing79%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%

G06TImage data processing or generation, in general3%

G11BInformation storage based on relative movement between record carrier and transducer1%

H03MCoding1%

H04NPictorial communication, e.g. television1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

PatentTitleYear

10,877,910Programmable event driven yield mechanism which may activate other threads2020 10,795,818Method and apparatus for ensuring real-time snoop latency2020 10,459,858Programmable event driven yield mechanism which may activate other threads2019 10,452,403Mechanism for instruction set based thread execution on a plurality of instruction sequencers2019 10,089,263Synchronization of interrupt processing to reduce power consumption2018 9,990,206Mechanism for instruction set based thread execution of a plurality of instruction sequencers2018 9,910,796'Programmable event driven yield mechanism which may activate other threads'2018 9,785,576'Hardware-assisted virtualization for implementing secure video output path'2017 9,733,937'Compare and exchange operation using sleep-wakeup mechanism'2017 9,720,697'Mechanism for instruction set based thread execution on a plurality of instruction sequencers'2017 9,600,283'Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode'2017 9,588,771'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'2017 9,459,874'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'2016 9,164,764'Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode'2015 9,032,232'Instruction for enabling a processor wait state'2015 8,990,597'Instruction for enabling a processor wait state'2015 8,984,199'Inter-processor interrupts'2015 8,914,618'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'2014 8,868,887'Programmable event driven yield mechanism which may activate other threads'2014 8,825,989'Technique to perform three-source operations'2014 8,812,792'Technique for using memory attributes'2014 8,762,694'Programmable event-driven yield mechanism'2014 8,762,692'Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode'2014 8,719,806'Speculative multi-threading for instruction prefetch and/or trace pre-build'2014 8,719,819'Mechanism for instruction set based thread execution on a plurality of instruction sequencers'2014 8,607,241'Compare and exchange operation using sleep-wakeup mechanism'2013 8,589,663'Technique to perform three-source operations'2013 8,560,781'Technique for using memory attributes'2013 8,510,536'Vector completion mask handling'2013 8,464,035'Instruction for enabling a processor wait state'2013 8,386,823'Method and apparatus for cost and power efficient, scalable operating system independent services'2013 8,332,619'Primitives to enhance thread-level speculation'2012 8,239,659'Vector completion mask handling'2012 8,171,321'Method and apparatus for cost and power efficient, scalable operating system independent services'2012 8,078,831'Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors'2011 8,074,274'User-level privilege management'2011 8,019,947'Technique for thread communication and synchronization'2011 7,991,965'Technique for using memory attributes'2011 7,913,064'Operation frame filtering, building, and execution'2011 7,882,339'Primitives to enhance thread-level speculation'2011 7,849,465'Programmable event driven yield mechanism which may activate service threads'2010 7,844,801'Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors'2010 7,818,547'Method and apparatus for efficient resource utilization for prescient instruction prefetch'2010 7,814,469'Speculative multi-threading for instruction prefetch and/or trace pre-build'2010 7,797,683'Decoupling the number of logical threads from the number of simultaneous physical threads in a processor'2010 7,757,045'Synchronizing recency information in an inclusive cache hierarchy'2010 7,743,233'Sequencer address management'2010 7,730,281'System and method for storing immediate data'2010 7,688,746'Method and system for dynamic resource allocation'2010 7,657,880'Safe store for speculative helper threads'2010 7,640,419'Method for and a trailing store buffer for use in memory renaming'2009 7,640,384'Queued locks using monitor-memory wait'2009 7,603,527'Resolving false dependencies of speculative load instructions'2009 7,587,584'Mechanism to exploit synchronization overhead to improve multithreaded performance'2009 7,562,206'Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions'2009 7,533,247'Operation frame filtering, building, and execution'2009 7,529,914'Method and apparatus for speculative execution of uncontended lock instructions'2009 7,529,913'Late allocation of registers'2009 7,523,465'Methods and apparatus for generating speculative helper thread spawn-target points'2009 7,516,313'Predicting contention in a processor'2009 7,502,912'Method and apparatus for rescheduling operations in a processor'2009 7,502,892'Decoupling request for ownership tag reads from data read operations'2009 7,500,049'Providing a backing store in user-level memory'2009 7,487,502'Programmable event driven yield mechanism which may activate other threads'2009 7,475,225'Method and apparatus for microarchitecture partitioning of execution clusters'2009 7,457,932'Load mechanism'2008 7,457,938'Staggered execution stack for vector processing'2008 7,404,067'Method and apparatus for efficient utilization for prescient instruction prefetch'2008 7,404,065'Flow optimization and prediction for VSSE memory operations'2008 7,328,293'Queued locks using monitor-memory wait'2008 7,321,963'System and method for storing immediate data'2008 7,213,093'Queued locks using monitor-memory wait'2007 7,174,428'Method and system for transforming memory location references in instructions'2007 7,149,883'Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue'2006 7,130,965'Apparatus and method for store address for store address prefetch and line locking'2006 7,114,057'System and method for storing immediate data'2006 7,085,889'Use of a context identifier in a cache memory'2006 6,990,551'System and method for employing a process identifier to minimize aliasing in a linear-addressed cache'2006 6,981,129'Breaking replay dependency loops in a processor using a rescheduled replay queue'2005 6,952,764'Stopping replay tornadoes'2005 6,912,648'Stick and spoke replay with selectable delays'2005 6,877,086'Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter'2005 6,798,364'Method and apparatus for variable length coding'2004 6,711,669'System and method for storing immediate data'2004 6,675,282'System and method for employing a global bit for page sharing in a linear-addressed cache'2004 6,662,173'Access control of a resource shared between components'2003 6,643,747'Processing requests to efficiently access a limited bandwidth storage area'2003 6,560,690'System and method for employing a global bit for page sharing in a linear-addressed cache'2003 6,338,132'System and method for storing immediate data'2002 6,105,111'Method and apparatus for providing a cache management technique'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2020Patents assigned to INTEL CORP (89)· patent assignee history

2000–2020Based in Hillsboro, OR, US· patent location history

2011–2018Patents assigned to HAMMARLUND PER (20)· patent assignee history

2011–2018Patents assigned to WANG HONG (12)· patent assignee history

2011–2017Patents assigned to CHINYA GAUTHAM (5)· patent assignee history

2011–2017Patents assigned to SHEN JOHN (5)· patent assignee history

2020Based in Sunnyvale, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	89	2000–2020
HAMMARLUND PERself	20	2011–2018
WANG HONG	12	2011–2018
CHINYA GAUTHAM	5	2011–2017
SHEN JOHN	5	2011–2017

Locations

Location	Patents	Span
Hillsboro, OR, US	89	2000–2020
Sunnyvale, California, US	1	2020