LexDanaLexDanabeta
Inventor

Joseph Zbiciak

Inventor
San Jose, CA, US

Overview

57→
Patents
2009–2021
Patent span
Physics
Primary field (CPC G)

Patents· 57 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing53%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use19%
H03MCoding8%
H03KPulse technique7%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%
H04LTransmission of digital information, e.g. telegraphic communication4%
H03HImpedance networks, e.g. resonant circuits2%
G06TImage data processing or generation, in general1%
PatentTitleYear
11,119,779Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization202111,113,057Streaming engine with cache-like stream data storage and lifetime tracking202111,099,933Streaming engine with error detection, correction and restart202111,074,190Slot/sub-slot prefetch architecture for multiple memory requestors202111,048,513Entering protected pipeline mode with clearing202111,042,468Tracking debug events from an autonomous module through a data pipeline202111,042,372Vector bit transpose202110,990,398Mechanism for interrupting and resuming execution on an unprotected pipeline processor202110,983,912Streaming engine with compressed encoding for loop circular buffer sizes202110,908,901Streaming engine with early exit from loop levels supporting early exit loops and irregular loops202110,891,231Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets202110,795,844Multicore bus architecture with non-blocking high performance transaction credit system202010,768,933Streaming engine with stream metadata saving for context switching202010,747,636Streaming engine with deferred exception reporting202010,713,174Streaming engine with early and late address and loop count registers to track architectural state202010,713,180Lookahead priority collection to support priority elevation202010,649,775Converting a stream of data using a lookaside buffer202010,628,156Vector SIMD VLIW data path architecture202010,620,957Method for forming constant extensions in the same execute packet in a VLIW processor202010,606,598Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization202010,606,596Cache preload operations using streaming engine202010,599,433Cache management operations using streaming engine202010,592,339Streaming engine with error detection, correction and restart202010,530,397Butterfly network on load data return202010,402,199Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor201910,394,718Slot/sub-slot prefetch architecture for multiple memory requestors201910,318,293Predication methods for vector processors201910,311,007Multicore bus architecture with non-blocking high performance transaction credit system201910,203,958Streaming engine with stream metadata saving for context switching201910,162,641Highly integrated scalable, flexible DSP megamodule architecture201810,083,035Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization201810,078,551Streaming engine with error detection, correction and restart201810,061,675Streaming engine with deferred exception reporting201810,037,439Secure master and secure guest endpoint security firewall201810,007,518Register file structures combining vector and scalar data with global and local accesses20189,965,395Memory attribute sharing between differing cache levels of multilevel cache20189,904,645'Multicore bus architecture with non-blocking high performance transaction credit system'20189,898,415'Slot/sub-slot prefetch architecture for multiple memory requestors'20189,606,803'Highly integrated scalable, flexible DSP megamodule architecture'20179,557,936'Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors'20179,465,753'Memory management unit that applies rules based on privilege identifier'20169,298,643'Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty'20169,239,798'Prefetcher with arbitrary downstream prefetch cancelation'20169,239,735'Compiler-control method for load speculation in a statically scheduled microprocessor'20169,183,084'Memory attribute sharing between differing cache levels of multilevel cache'20159,110,845'Memory management unit that applies rules based on privilege identifier'20159,075,744'Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty'20158,904,260'Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme'20148,683,134'Upgrade of low priority prefetch requests to high priority real requests in shared memory controller'20148,683,133'Termination of prefetch requests in shared memory controller'20148,656,105'Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers'20148,607,000'Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU'20138,560,896'Priority based exception mechanism for multi-level cache controller'20138,301,928'Automatic wakeup handling on access in shared memory controller'20128,201,004'Entry/exit control to/from a low power state in a complex multi level memory system'20128,112,652'Multiprocessor system power management of shared memories powering down memory bank only when all processors indicate not powering that memory bank'20127,546,391'Direct memory access channel controller with quick channels, event queue and active channel memory protection'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2021Patents assigned to TEXAS INSTRUMENTS INC (57)· patent assignee history
2009–2018Based in Arlington, TX, US· patent location history
2012–2015Patents assigned to DAMODARAN RAGURAM (5)· patent assignee history
2012–2014Patents assigned to ANAND ALOK (4)· patent assignee history
2013–2015Patents assigned to ZBICIAK JOSEPH RAYMOND MICHAEL (6)· patent assignee history
2013–2015Patents assigned to CHACHAD ABHIJEET ASHOK (5)· patent assignee history
2016–2020Based in Farmers Branch, TX, US· patent location history
2018–2021Based in San Jose, CA, US· patent location history
2020–2021Based in Alviso, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC572009–2021
ZBICIAK JOSEPH RAYMOND MICHAELself62013–2015
CHACHAD ABHIJEET ASHOK52013–2015
DAMODARAN RAGURAM52012–2015
ANAND ALOK42012–2014
Locations
LocationPatentsSpan
San Jose, California, US232018–2021
Arlington, Texas, US162009–2018
Farmers Branch, Texas, US142016–2020
Alviso, California, US42020–2021