Inventor

Peter B. Gillingham

Inventor

Kanata, CA

Overview

1987–2021

Patent span

Physics

Primary field (CPC G)

Patents· 137 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores39%

G06FElectric digital data processing14%

H03KPulse technique10%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%

G05FSystems for regulating electric or magnetic variables3%

H04LTransmission of digital information, e.g. telegraphic communication3%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%

H01LSemiconductor devices3%

PatentTitleYear

11,049,574Non-volatile semiconductor memory having multiple external power supplies2021 10,866,739Clock mode determination in a memory system2020 10,706,943Non-volatile semiconductor memory having multiple external power supplies2020 10,489,057Clock mode determination in a memory system2019 10,199,113Non-volatile semiconductor memory having multiple external power supplies2019 10,140,028Clock mode determination in a memory system2018 9,977,731Bridging device having a configurable virtual page size2018 9,971,518Clock mode determination in a memory system2018 RE046819Synchronous memory read data capture2018 9,928,918'Non-volatile semiconductor memory having multiple external power supplies'2018 9,875,835Optical telescope fibre positioning devices2018 9,780,073'Using interrupted through-silicon-vias in integrated circuits adapted for stacking'2017 9,740,407'Clock mode determination in a memory system'2017 9,576,675'Non-volatile semiconductor memory having multiple external power supplies'2017 9,552,889'Clock mode determination in a memory system'2017 9,384,847'Clock mode determination in a memory system'2016 9,348,786'Semiconductor memory device with plural memory die and controller die'2016 9,245,640'Non-volatile semiconductor memory having multiple external power supplies'2016 9,236,095'Method and apparatus for sharing internal power supplies in integrated circuit devices'2016 9,190,369'Using interrupted Through-Silicon-Vias in integrated circuits adapted for stacking'2015 9,177,863'Multi-chip package with offset die stacking and method of making same'2015 9,148,277'Clock reproducing and timing method in a system having a plurality of devices'2015 9,042,199'Clock mode determination in a memory system'2015 8,966,208'Semiconductor memory device with plural memory die and controller die'2015 8,898,415'Simultaneous read and write data transfer'2014 8,880,970'Error detection method and a system including one or more memory devices'2014 8,854,915'Clock mode determination in a memory system'2014 8,836,148'Interposer for stacked semiconductor devices'2014 8,825,966'Reduced pin count interface'2014 8,781,053'Clock reproducing and timing method in a system having a plurality of devices'2014 8,780,622'Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance'2014 8,767,430'Configurable module and memory subsystem'2014 8,711,573'Using interrupted through-silicon-vias in integrated circuits adapted for stacking'2014 8,654,573'High bandwidth memory interface'2014 8,644,108'Clock mode determination in a memory system'2014 8,638,638'Delay locked loop implementation in a synchronous dynamic random access memory'2014 8,625,352'Method and apparatus for sharing internal power supplies in integrated circuit devices'2014 8,619,473'Non-volatile semiconductor memory having multiple external power supplies'2013 RE044589'Single chip frame buffer and graphics accelerator'2013 8,549,209'Bridging device having a configurable virtual page size'2013 8,521,980'Simultaneous read and write data transfer'2013 8,504,789'Bridging device having a frequency configurable clock domain'2013 8,503,211'Configurable module and memory subsystem'2013 8,502,368'Multi-chip package with offset die stacking'2013 8,471,591'Termination circuit for on-die termination'2013 8,432,767'Clock mode determination in a memory system'2013 8,432,729'Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance'2013 8,400,781'Using interrupted through-silicon-vias in integrated circuits adapted for stacking'2013 8,369,182'Delay locked loop implementation in a synchronous dynamic random access memory'2013 8,300,471'Non-volatile semiconductor memory having multiple external power supplies'2012 8,266,372'High bandwidth memory interface'2012 8,250,297'High bandwidth memory interface'2012 8,194,456'Non-volatile semiconductor memory having multiple external power supplies'2012 8,122,202'Reduced pin count interface'2012 8,086,813'Synchronous memory read data capture'2011 8,063,658'Termination circuit for on-die termination'2011 8,023,519'Dense mode coding scheme'2011 7,885,140'Clock mode determination in a memory system'2011 RE041565'Single chip frame buffer and graphics accelerator'2010 7,765,376'Apparatuses for synchronous transfer of information'2010 7,685,393'Synchronous memory read data capture'2010 7,639,540'Non-volatile semiconductor memory having multiple external power supplies'2009 7,633,960'Dense mode coding scheme'2009 7,599,246'Delay locked loop implementation in a synchronous dynamic random access memory'2009 7,561,454'Compare circuit for a content addressable memory cell'2009 RE040552'Dynamic random access memory using imperfect isolating transistors'2008 7,382,638'Matchline sense circuit and method'2008 RE040326'Single chip frame buffer and graphics accelerator'2008 7,346,009'Dense mode coding scheme'2008 RE040075'Method of multi-level storage in DRAM and apparatus thereof'2008 7,304,876'Compare circuit for a content addressable memory cell'2007 7,299,330'High bandwidth memory interface'2007 7,251,148'Matchline sense circuit and method'2007 7,120,040'Ternary CAM cell for reduced matchline capacitance'2006 6,992,950'Delay locked loop implementation in a synchronous dynamic random access memory'2006 6,987,682'Matchline sense circuit and method'2006 6,980,448'DRAM boosted voltage supply'2005 6,779,097'High bandwidth memory interface'2004 6,768,659'Circuit and method for reducing power usage in a content addressable memory'2004 6,744,688'Searchline control circuit and power reduction method'2004 6,708,250'Circuit and method for performing variable width searches in a content addressable memory'2004 6,657,919'Delayed locked loop implementation in a synchronous dynamic random access memory'2003 6,657,918'Delayed locked loop implementation in a synchronous dynamic random access memory'2003 6,614,705'Dynamic random access memory boosted voltage supply'2003 6,584,003'Low power content addressable memory architecture'2003 6,580,654'Boosted voltage supply'2003 6,546,476'Read/write timing for maximum utilization of bi-directional read/write bus'2003 6,529,397'Memory-logic semiconductor device'2003 6,522,596'Searchline control circuit and power reduction method'2003 6,510,503'High bandwidth memory interface'2003 RE037944'Single chip frame buffer and graphics accelerator'2002 6,483,733'Dynamic content addressable memory cell'2002 6,442,644'Memory system having synchronous-link DRAM (SLDRAM) devices and controller'2002 RE037641'Dynamic random access memory using imperfect isolating transistors'2002 6,320,777'Dynamic content addressable memory cell'2001 6,314,052'Delayed locked loop implementation in a synchronous dynamic random access memory'2001 6,266,750'Variable length pipeline with parallel functional units'2001 6,249,827'Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock lines'2001 6,236,581'High voltage boosted word line supply charge pump and regulator for DRAM'2001 6,205,083'Delayed locked loop implementation in a synchronous dynamic random access memory'2001 RE037072'Method of multi-level storage in DRAM and apparatus thereof'2001 6,182,257'BIST memory test system'2001 6,088,774'Read/write timing for maximum utilization of bidirectional read/write bus'2000 6,067,272'Delayed locked loop implementation in a synchronous dynamic random access memory'2000 6,058,050'Precharge-enable self boosting word line driver for an embedded DRAM'2000 6,055,201'High voltage boosted word line supply charge pump and regulator for DRAM'2000 5,923,596'Precharge-enable self boosting word line driver for an embedded DRAM'1999 5,903,511'Flexible DRAM array'1999 5,854,763'Integrated circuit with non-binary decoding and data access'1998 5,835,438'Precharge-enable self boosting word line driver for an embedded DRAM'1998 5,828,620'High voltage boosted word line supply charge pump and regulator for DRAM'1998 5,796,673'Delay locked loop implementation in a synchronous dynamic random access memory'1998 5,724,286'Flexible DRAM array'1998 5,715,200'Memory devices'1998 5,712,823'Flexible dram array'1998 5,708,619'Column redundancy scheme for DRAM using normal and redundant column decoders programmed with defective array address and defective column address'1998 5,699,313'High voltage boosted word line supply charge pump and regulator for dram'1997 5,694,143'Single chip frame buffer and graphics accelerator'1997 5,694,355'Memory cell and wordline driver for embedded DRAM in ASIC process'1997 5,625,601'DRAM page copy method'1997 5,612,912'Method of multilevel DRAM sense and restore'1997 5,600,598'Memory cell and wordline driver for embedded DRAM in ASIC process'1997 5,574,681'Method for DRAM sensing current control'1996 5,546,350'RAM variable size block write'1996 5,532,955'Method of multilevel dram sense and restore'1996 5,469,401'Column redundancy scheme for DRAM using normal and redundant column decoders programmed with defective array address and defective column address'1995 5,414,662'Dynamic random access memory using imperfect isolating transistors'1995 5,406,523'High voltage boosted word line supply charge pump and regulator for DRAM'1995 5,305,283'Dram column address latching technique'1994 5,283,761'Method of multi-level storage in DRAM'1994 5,267,201'High voltage boosted word line supply charge pump regulator for DRAM'1993 5,198,708'Transition detection circuit'1993 5,144,223'Bandgap voltage generator'1992 5,021,681'Jiter-invariant switched capacitor pulse shaper'1991 4,803,705'Analog phase locked loop'1989 4,751,666'Switched capacitor finite impulse response filter'1988 4,653,017'Decimating filter'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–2021Based in Ottawa, CA· patent location history

1991–2018Based in Kanata, CA· patent location history

1994–2021Patents assigned to MOSAID TECHNOLOGIES INC (97)· patent assignee history

2000–2003Patents assigned to ADVANCED MEMORY INTERNATIONAL (5)· patent assignee history

2011–2015Patents assigned to GILLINGHAM PETER (12)· patent assignee history

2013–2014Patents assigned to GILLINGHAM PETER B (11)· patent assignee history

2014–2021Patents assigned to CONVERSANT INTELLECTUAL PROPERTY MAN INC (28)· patent assignee history

2018Based in Canberra, AU· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MOSAID TECHNOLOGIES INC	97	1994–2021
CONVERSANT INTELLECTUAL PROPERTY MAN INC	28	2014–2021
GILLINGHAM PETERself	12	2011–2015
GILLINGHAM PETER Bself	11	2013–2014
ADVANCED MEMORY INTERNATIONAL	5	2000–2003

Locations

Location	Patents	Span
Kanata, CA	101	1991–2018
Ottawa, CA	35	1987–2021
Canberra, AU	1	2018