Inventor

Grant M. Kloster

Inventor

Lake Oswego, OR, US

Overview

2003–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 55 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1044%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%

H10DInorganic electric semiconductor devices6%

C23CCoating metallic material5%

H01LSemiconductor devices4%

Y10TTechnical subjects covered by former us classification3%

B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%

B81BMicrostructural devices or systems, e.g. micromechanical devices2%

B82YSpecific uses or applications of nanostructures1%

C03CChemical composition of glasses, glazes or vitreous enamels1%

PatentTitleYear

10,756,215Selective deposition utilizing sacrificial blocking layers for semiconductor devices2020 10,396,176Selective gate spacers for semiconductor devices2019 10,243,080Selective deposition utilizing sacrificial blocking layers for semiconductor devices2019 9,932,671Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD)2018 9,530,733'Forming layers of materials over small regions by selective chemical reaction including limiting enchroachment of the layers over adjacent regions'2016 8,154,121'Polymer interlayer dielectric and passivation materials for a microelectronic device'2012 7,658,975'Sealing porous dielectric materials'2010 7,560,165'Sealing porous dielectric materials'2009 7,544,896'Forming a porous dielectric layer and structures formed thereby'2009 7,456,490'Sealing porous dielectrics with silane coupling reagents'2008 7,422,020'Aluminum incorporation in porous dielectric for improved mechanical properties of patterned dielectric'2008 7,365,375'Organic-framework zeolite interlayer dielectrics'2008 7,354,862'Thin passivation layer on 3D devices'2008 7,344,972'Photosensitive dielectric layer'2008 7,335,586'Sealing porous dielectric material using plasma-induced surface polymerization'2008 7,332,406'Air gap interconnect structure and method'2008 7,320,928'Method of forming a stacked device filler'2008 7,303,989'Using zeolites to improve the mechanical strength of low-k interlayer dielectrics'2007 7,294,568'Formation of air gaps in an interconnect structure using a thin permeable hard mask and resulting structures'2007 7,294,934'Low-K dielectric structure and method'2007 7,238,604'Forming thin hard mask over air gap or porous dielectric'2007 7,239,019'Selectively converted inter-layer dielectric'2007 7,220,668'Method of patterning a porous dielectric material'2007 7,217,595'Sealed three dimensional metal bonded integrated circuits'2007 7,214,605'Deposition of diffusion barrier'2007 7,214,594'Method of making semiconductor device using a novel interconnect cladding layer'2007 7,186,637'Method of bonding semiconductor devices'2007 7,179,755'Forming a porous dielectric layer and structures formed thereby'2007 7,180,180'Stacked device underfill and a method of fabrication'2007 7,169,715'Forming a dielectric layer using porogens'2007 7,164,206'Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer'2007 7,145,245'Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrateâ€”therein'2006 7,138,158'Forming a dielectric layer using a hydrocarbon-containing precursor'2006 7,122,481'Sealing porous dielectrics with silane coupling reagents'2006 7,087,538'Method to fill the gap between coupled wafers'2006 7,034,399'Forming a porous dielectric layer'2006 7,030,040'Selectively growing a polymeric material on a semiconductor substrate'2006 7,018,918'Method of forming a selectively converted inter-layer dielectric using a porogen material'2006 6,992,391'Dual-damascene interconnects without an etch stop layer by alternating ILDs'2006 6,984,873'Method of forming a stacked device filler'2006 6,964,919'Low-k dielectric film with good mechanical strength'2005 6,946,384'Stacked device underfill and a method of fabrication'2005 6,943,121'Selectively converted inter-layer dielectric'2005 6,930,391'Method for alloy-electroplating group IB metals with refractory metals for interconnections'2005 6,905,958'Protecting metal conductors with sacrificial organic monolayers'2005 6,903,461'Semiconductor device having a region of a material which is vaporized upon exposing to ultraviolet radiation'2005 6,867,125'Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material'2005 6,867,473'Plating a conductive material on a dielectric material'2005 6,861,332'Air gap interconnect method'2005 6,846,755'Bonding a metal component to a low-k dielectric material'2005 6,737,365'Forming a porous dielectric layer'2004 6,734,118'Dielectric material treatment'2004 6,734,094'Method of forming an air gap within a structure by exposing an ultraviolet sensitive material to ultraviolet radiation'2004 6,682,989'Plating a conductive material on a dielectric material'2004 6,605,549'Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2020Patents assigned to INTEL CORP (55)· patent assignee history

2003–2020Based in Lake Oswego, OR, US· patent location history

2006–2007Based in Hillsboro, OR, US· patent location history

2007Based in Hillboro, OR, US· patent location history

2012Patents assigned to HAVERTY MICHAEL (1)· patent assignee history

2012Patents assigned to INGERLY DOUG (1)· patent assignee history

2012Patents assigned to KLOSTER GRANT (1)· patent assignee history

2012Patents assigned to SHAH KUNAL (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	55	2003–2020
HAVERTY MICHAEL	1	2012
INGERLY DOUG	1	2012
KLOSTER GRANTself	1	2012
SHAH KUNAL	1	2012

Locations

Location	Patents	Span
Lake Oswego, OR, US	52	2003–2020
Hillsboro, OR, US	2	2006–2007
Hillboro, OR, US	1	2007