Inventor
Joseph Jun Cao
Inventor
Los Gatos, CA, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing46%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use19%
H03KPulse technique12%
G11CStatic stores8%
H03MCoding7%
G05FSystems for regulating electric or magnetic variables3%
H04LTransmission of digital information, e.g. telegraphic communication3%
G05BControl or regulating systems in general2%
PatentTitleYear
10,198,310Providing error correcting code (ECC) capability for memory20199,958,884Universal adaptive voltage scaling system20189,524,255'System and method for automatic DQS gating based on counter signal'20169,507,742'Variable length arbitration'20169,411,753'Systems and methods for dynamically determining a priority for a queue of commands'20169,396,146'Timing-budget-based quality-of-service control for a system-on-chip'20169,367,347'Systems and methods for command execution order control in electronic systems'20169,285,824'Systems and methods for DQS gating'20169,264,030'Adaptive voltage scaling using a delay line'20169,264,368'Chip-to-chip communications'20169,223,327'Universal adaptive voltage scaling system'20159,189,329'Generating error correcting code (ECC) data using an ECC corresponding to an identified ECC protection level'20159,183,078'Providing error checking and correcting (ECC) capability for memory'20159,146,690'Systems and methods for dynamic priority control'20159,116,836'Tunneling transaction packets'20158,996,844'Apparatus and method for accessing non-overlapping portions of memory according to respective orders of dimensions'20158,959,417'Providing low-latency error correcting code capability for memory'20158,949,474'Method for inter-chip and intra-chip addressing using port identifiers and address mapping'20158,935,596'System and methods for storing data encoded with error information in a storage medium'20158,826,047'Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers'20148,717,089'Adaptive voltage scaling using a delay line'20148,621,181'System and method for accessing distinct regions of memory using multiple mapping modes, each of the mapping modes having a predetermined order of dimensions for a respective region of the memory'20138,519,781'Adaptive voltage scaling using a delay line'20138,448,001'System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device'20138,402,249'System and method for mixed-mode SDRAM address mapping'20138,378,738'Adaptive voltage scaling using a delay line'20138,352,837'System and methods for storing data encoded with error information in a storage medium'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2019Patents assigned to MARVELL INT LTD (19)· patent assignee history
2013–2016Patents assigned to CAO JOSEPH JUN (5)· patent assignee history
2013–2016Patents assigned to ZHU JUN (5)· patent assignee history
2013–2016Patents assigned to LU SHENG (2)· patent assignee history
2013–2019Based in Los Gatos, CA, US· patent location history
2015–2016Patents assigned to MARVELL WORLD TRADE LTD (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MARVELL INT LTD | 19 | 2013–2019 |
| MARVELL WORLD TRADE LTD | 8 | 2015–2016 |
| CAO JOSEPH JUNself | 5 | 2013–2016 |
| ZHU JUN | 5 | 2013–2016 |
| LU SHENG | 2 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Gatos, California, US | 27 | 2013–2019 |