Inventor
Saurabh Garg
Inventor
San Jose, CA, US
Overview
Patents· 56 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing26%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%
H01JElectric discharge tubes or discharge lamps7%
H04WWireless communication networks7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
C23CCoating metallic material6%
H01LSemiconductor devices6%
H04LTransmission of digital information, e.g. telegraphic communication3%
B05BSpraying apparatus2%
H10BElectronic memory devices2%
PatentTitleYear
10,853,272Memory access protection apparatus and methods for memory mapped access between independently operable processors202010,846,237Methods and apparatus for locking at least a portion of a shared memory resource202010,845,868Methods and apparatus for running and booting an inter-processor communication link between independently operable processors202010,846,224Methods and apparatus for control of a jointly shared memory-mapped region202010,841,880Apparatus and methods for wake-limiting with an inter-device communication link202010,838,450Methods and apparatus for synchronization of time between independently operable processors202010,789,198Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors202010,789,110Methods and apparatus for correcting out-of-order data transactions between processors202010,775,871Methods and apparatus for providing individualized power control for peripheral sub-systems202010,776,973Vanishing point computation for single vanishing point images202010,719,376Methods and apparatus for multiplexing data flows via a single data structure202010,684,670Methods and apparatus for managing power with an inter-processor communication link between independently operable processors202010,591,976Methods and apparatus for providing peripheral sub-system stability202010,585,699Methods and apparatus for verifying completion of groups of data transactions between processors202010,572,390Methods and apparatus for loading firmware on demand202010,558,580Methods and apparatus for loading firmware on demand202010,551,906Methods and apparatus for running and booting inter-processor communication link between independently operable processors202010,552,352Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link202010,551,902Methods and apparatus for providing access to peripheral sub-system registers202010,551,328Ceramic ring test device202010,489,223Methods and apparatus for scheduling time sensitive operations among independent processors201910,430,352Methods and apparatus for reduced overhead data transfer with a shared ring buffer201910,432,705Configuring control devices operable for a load control environment201910,372,637Methods and apparatus for aggregating packet transfer over a virtual bus interface201910,372,199Apparatus for managing power and running and booting an inter-processor communication link between independently operable processors201910,354,843Chemical control features in wafer process equipment201910,346,226Methods and apparatus for transmitting time sensitive data over a tunneled bus interface201910,331,612Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors201910,268,261Methods and apparatus for managing power with an inter-processor communication link between independently operable processors201910,198,364Memory access protection apparatus and methods for memory mapped access between independently operable processors201910,191,859Memory access protection apparatus and methods for memory mapped access between independently operable processors201910,191,852Methods and apparatus for locking at least a portion of a shared memory resource201910,085,214Apparatus and methods for wake-limiting with an inter-device communication link201810,078,361Methods and apparatus for running and booting an inter-processor communication link between independently operable processors201810,056,233RPS assisted RF plasma source for semiconductor processing201810,042,794Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link201810,032,606Semiconductor processing with DC assisted RF power for improved control20189,978,564Chemical control features in wafer process equipment20189,971,397Methods and apparatus for managing power with an inter-processor communication link between independently operable processors20189,846,130Ceramic ring test device20179,842,036'Methods and apparatus for controlled recovery of error information between independently operable processors'20179,830,289Methods and apparatus for aggregating packet transfer over a virtual bus interface20179,798,377'Methods and apparatus for recovering errors with an inter-processor communication link between independently operable processors'20179,741,545'RPS assisted RF plasma source for semiconductor processing'20179,502,218'RPS assisted RF plasma source for semiconductor processing'20169,384,997'Dry-etch selectivity'20169,373,517'Semiconductor processing with DC assisted RF power for improved control'20169,255,285'Fermentation medias and processes thereof'20169,182,932'Systems and methods for printing content associated with a website'20159,132,436'Chemical control features in wafer process equipment'20158,969,212'Dry-etch selectivity'20158,927,256'Fermentation medias and processes thereof'20157,987,304'Association using USB video adapter'20117,937,514'CWUSB host management system'20117,865,642'Pre-association for CWUSB'20117,580,424'System and method for providing real-time and non-real-time services over a communications system'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011Patents assigned to REALTEK SEMICONDUCTOR CORP (3)· patent assignee history
2011Based in Irvine, CA, US· patent location history
2015–2020Patents assigned to APPLIED MATERIALS INC (12)· patent assignee history
2015–2016Patents assigned to BIOCON LTD (2)· patent assignee history
2015Patents assigned to GARG SAURABH (2)· patent assignee history
2015–2016Based in Santa Clara, CA, US· patent location history
2016–2020Based in San Jose, CA, US· patent location history
2017–2020Patents assigned to APPLE INC (35)· patent assignee history
2017–2020Based in Chicago, IL, US· patent location history
2018–2020Based in Cupertino, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLE INC | 35 | 2017–2020 |
| APPLIED MATERIALS INC | 12 | 2015–2020 |
| REALTEK SEMICONDUCTOR CORP | 3 | 2011 |
| BIOCON LTD | 2 | 2015–2016 |
| GARG SAURABHself | 2 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 27 | 2016–2020 |
| Cupertino, California, US | 13 | 2018–2020 |
| Santa Clara, California, US | 4 | 2015–2016 |
| Irvine, California, US | 3 | 2011 |
| Chicago, Illinois, US | 2 | 2017–2020 |