Inventor
James Roberts
Inventor
Austin, TX, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing91%
G06TImage data processing or generation, in general6%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%
PatentTitleYear
10,515,011Compression status bit cache and backing store20198,949,541'Techniques for evicting dirty data from a cache using a notification sorter and count thresholds'20158,874,844'Padding buffer requests to avoid reads of invalid data'20148,868,838'Multi-class data cache policies'20148,862,823'Compression status caching'20148,700,862'Compression status bit cache and backing store'20148,627,041'Efficient line and page organization for compression status bit caching'20148,595,437'Compression status bit cache with deterministic isochronous latency'20138,504,773'Storing dynamically sized buffers within a cache'20138,464,001'Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism'20138,341,358'System and method for cleaning dirty data in a cache via frame buffer logic'20128,271,734'Method and system for converting data formats using a shared cache coupled between clients and an external memory'20128,244,984'System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy'20128,234,478'Using a data cache array as a DRAM load/store buffer'20128,156,404'L2 ECC implementation'20128,135,926'Cache-based control of atomic operations in conjunction with an external ALU block'20128,131,931'Configurable cache occupancy policy'20128,108,610'Cache-based control of atomic operations in conjunction with an external ALU block'20128,099,650'L2 ECC implementation'20128,060,700'System, method and frame buffer logic for evicting dirty data from a cache using counters and data types'20117,024,545'Hybrid branch prediction device with two levels of branch prediction cache'20066,502,188'Dynamic classification of conditional branches in global history branch prediction'20026,427,192'Method and apparatus for caching victimized branch predictions'20026,393,536'Load/store unit employing last-in-buffer indication for rapid load-hit-store'20026,279,106'Method for reducing branch target storage by calculating direct branch targets on the fly'20016,275,927'Compressing variable-length instruction prefix bytes'20016,192,465'Using multiple decoders and a reorder queue to decode instructions out of order'20015,845,323'Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time'19985,752,069'Superscalar microprocessor employing away prediction structure'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2019Based in Austin, TX, US· patent location history
2011–2019Patents assigned to NVIDIA CORP (20)· patent assignee history
2011–2015Patents assigned to ROBERTS JAMES (19)· patent assignee history
2011–2015Patents assigned to GLASCO DAVID B (18)· patent assignee history
2011–2015Patents assigned to HOLMQVIST PETER B (18)· patent assignee history
2011–2015Patents assigned to LYNCH GEORGE R (18)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NVIDIA CORP | 20 | 2011–2019 |
| ROBERTS JAMESself | 19 | 2011–2015 |
| GLASCO DAVID B | 18 | 2011–2015 |
| HOLMQVIST PETER B | 18 | 2011–2015 |
| LYNCH GEORGE R | 18 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 29 | 1998–2019 |