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Inventor

Anthony M. Chiu

Inventor
Richardson, TX, US

Overview

77→
Patents
1987–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H05KPrinted circuits14%
Y10TTechnical subjects covered by former us classification13%
Y02PClimate change mitigation technologies in the production or processing of goods6%
G06VImage or video recognition or understanding5%
H10DInorganic electric semiconductor devices5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H01MProcesses or means, e.g. batteries, for the direct conversion of chemical energy into electrical energy3%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
G01RMeasuring electric variables3%
PatentTitleYear
10,177,064Air cavity package20199,936,587Method of fabricating a multi-channel modulator driver with enclosure20189,899,292'Top-side cooling of RF products in air cavity composite packages'20189,113,549'Enclosure for a multi-channel modulator driver'20158,524,531'System and method for improving solder joint reliability in an integrated circuit package'20138,367,271'Fuel cell device'20138,330,258'System and method for improving solder joint reliability in an integrated circuit package'20128,202,668'Fuel cell device'20128,202,667'Fuel cell device'20128,178,250'Fuel cell device'20128,163,645'Method for providing a redistribution metal layer in an integrated circuit'20127,786,582'System for providing a redistribution metal layer in an integrated circuit'20107,595,017'Method for using a pre-formed film in a transfer molding process for an integrated circuit'20097,547,483'Fuel cell device'20097,534,716'System and method for venting pressure from an integrated circuit package sealed with a lid'20097,482,260'System and method for increasing the strength of a bond made by a small diameter wire in ball bonding'20097,382,056'Integrated passive devices'20087,323,114'Method of making optical elements for an optical disc system'20087,265,452'System and method for increasing the strength of a bond made by a small diameter wire in ball bonding'20077,202,110'Embedded flat film molding'20077,196,425'Copper interposer for reducing warping of integrated circuit packages and method of making IC packages'20077,126,210'System and method for venting pressure from an integrated circuit package sealed with a lid'20067,109,574'Integrated circuit package with exposed die surfaces and auxiliary attachment'20067,098,065'Integrated lid formed on MEMS device'20067,096,581'Method for providing a redistribution metal layer in an integrated circuit'20067,068,270'Design of integrated circuit package using parametric solids modeller'20067,061,091'Surface mount package with integral electro-static charge dissipating ring using lead frame as ESD device'20067,006,426'Integrated optical unit for use with miniature optical discs'20066,951,125'System and method for aligning an integrated circuit die on an integrated circuit substrate'20056,919,230'Method of eliminating uncontrolled voids in sheet adhesive layer'20056,908,787'System and method for increasing the strength of a bond made by a small diameter wire in ball bonding'20056,900,508'Embedded flat film molding'20056,818,963'Surface mount package for linear array sensors'20046,787,388'Surface mount package with integral electro-static charge dissipating ring using lead frame as ESD device'20046,769,174'Leadframeless package structure and method'20046,771,500'System and method for direct convective cooling of an exposed integrated circuit die surface'20046,707,163'Method of eliminating uncontrolled voids in sheet adhesive layer'20046,700,190'Integrated circuit device with exposed upper and lower die surfaces'20046,686,546'Static charge dissipation for an active circuit surface'20046,600,227'System and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package'20036,437,984'Thermally enhanced chip scale package'20026,414,849'Low stress and low profile cavity down flip chip and wire bond BGA package'20026,410,985'Silver metallization by damascene method'20026,372,543'Wrap-around interconnect for fine pitch ball grid array'20026,326,679'Low cost heat sink for packaged semiconductor device'20016,326,647'Packaging and mounting of spherical semiconductor devices'20016,228,679'Apparatus and method for automating the underfill of flip-chip devices'20016,214,643'Stress reduction for flip chip package'20016,121,678'Wrap-around interconnect for fine pitch ball grid array'20006,113,399'Low-profile socketed packaging system with land-grid array and thermally conductive slug'20006,100,194'Silver metallization by damascene method'20006,067,025'Apparatus and method for detecting the height above a silicon surface'20006,011,301'Stress reduction for flip chip package'20005,955,784'Ball contact for flip-chip device'19995,942,798'Apparatus and method for automating the underfill of flip-chip devices'19995,849,132'Ball contact for flip-chip devices'19985,832,596'Method of making multiple-bond shelf plastic package'19985,808,870'Plastic pin grid array package'19985,805,419'Low-profile socketed packaging system with land-grid array and thermally conductive slug'19985,696,029'Process for manufacturing a lead frame'19975,677,247'Low-profile socketed packaging system with land-grid array and thermally conductive slug'19975,661,900'Method of fabricating an ultrasonically welded plastic support ring'19975,555,488'Integrated circuit device having improved post for surface-mount package'19965,532,614'Wafer burn-in and test system'19965,444,366'Wafer burn-in and test system'19955,358,905'Semiconductor device having die pad locking to substantially reduce package cracking'19945,358,598'Folded bus bar leadframe and method of making'19945,359,493'Three dimensional multi-chip module with integral heat sink'19945,307,010'Wafer burn-in and test system'19945,286,999'Folded bus bar leadframe'19945,243,497'Chip on board assembly'19935,239,199'Vertical lead-on-chip package'19935,204,287'Integrated circuit device having improved post for surface-mount package'19935,192,681'Low cost erasable programmable read only memory package'19935,163,232'Semiconductor lead planarity checker'19925,136,367'Low cost erasable programmable read only memory package'19924,639,664'Apparatus for testing a plurality of integrated circuits in parallel'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–2006Patents assigned to TEXAS INSTRUMENTS INC (21)· patent assignee history
1987–2019Based in Richardson, TX, US· patent location history
1998–2013Patents assigned to ST MICROELECTRONICS INC (49)· patent assignee history
2012–2013Patents assigned to CHIU ANTHONY M (6)· patent assignee history
2015–2018Patents assigned to TRIQUINT SEMICONDUCTOR INC (2)· patent assignee history
2018–2019Patents assigned to QORVO US INC (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ST MICROELECTRONICS INC491998–2013
TEXAS INSTRUMENTS INC211987–2006
CHIU ANTHONY Mself62012–2013
QORVO US INC32018–2019
TRIQUINT SEMICONDUCTOR INC22015–2018
Locations
LocationPatentsSpan
Richardson, Texas, US771987–2019