Inventor
Michael W. Leddige
Inventor
Beaverton, OR, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H05Kprimary
H05KPrinted circuits30%
G11CStatic stores19%
G06FElectric digital data processing16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
Y02PClimate change mitigation technologies in the production or processing of goods7%
H04LTransmission of digital information, e.g. telegraphic communication5%
H01RElectrically-conductive connections4%
G02BOptical elements, systems or apparatus2%
H03MCoding2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
PatentTitleYear
10,078,612Mode selective balanced encoded interconnect20189,910,814'Method, apparatus and system for single-ended communication of transaction layer packets'20189,632,961'Crosstalk aware decoding for a data bus'20179,391,378'High bandwidth connector for internal and external IO interfaces'20169,330,039'Crosstalk aware encoding for a data bus'20168,775,991'Interchangeable connection arrays for double-sided DIMM placement'20148,649,262'Dynamic configuration of potential links between processing elements'20148,631,208'Providing address range coherency capability to a device'20148,438,515'Interchangeable connection arrays for double-sided DIMM placement'20138,099,687'Interchangeable connection arrays for double-sided DIMM placement'20127,772,708'Stacking integrated circuit dies'20107,514,773'Systems and arrangements for interconnecting integrated circuit dies'20097,402,048'Technique for blind-mating daughtercard to mainboard'20087,194,572'Memory system and method to reduce reflection and signal degradation'20077,133,962'Circulator chain memory command and address bus topology'20066,918,078'Systems with modules sharing terminations'20056,891,899'System and method for bit encoding to increase data transfer rate'20056,788,222'Low weight data encoding for minimal power delivery impact'20046,724,082'Systems having modules with selectable on die terminations'20046,711,640'Split delay transmission line'20046,708,243'Computer assembly with stub traces coupled to vias to add capacitance at the vias'20046,686,762'Memory module using DRAM package to match channel impedance'20046,631,083'Systems with modules and clocking therefore'20036,587,912'Method and apparatus for implementing multiple memory buses on a memory module'20036,539,449'Capacitively loaded continuity module'20036,515,555'Memory module with parallel stub traces'20036,477,614'Method for implementing multiple memory buses on a memory module'20026,366,466'Multi-layer printed circuit board with signal traces of varying width'20026,362,973'Multilayer printed circuit board with placebo vias for controlling interconnect skew'20026,353,539'Method and apparatus for matched length routing of back-to-back package placement'20026,144,576'Method and apparatus for implementing a serial memory architecture'20006,111,205'Via pad geometry supporting uniform transmission line structures'20006,005,776'Vertical connector based packaging solution for integrated circuits'19995,513,073'Optical device heat spreader and thermal isolation apparatus'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996Based in Rochester, MN, US· patent location history
1999–2018Patents assigned to INTEL CORP (33)· patent assignee history
1999–2018Based in Beaverton, OR, US· patent location history
2012–2014Patents assigned to LEDDIGE MICHAEL W (4)· patent assignee history
2012–2013Patents assigned to BAINS KULJIT SINGH (2)· patent assignee history
2012–2013Patents assigned to SPRIETSMA JOHN THOMAS (2)· patent assignee history
2016Patents assigned to CHEN KUAN-YU (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 33 | 1999–2018 |
| LEDDIGE MICHAEL Wself | 4 | 2012–2014 |
| BAINS KULJIT SINGH | 2 | 2012–2013 |
| SPRIETSMA JOHN THOMAS | 2 | 2012–2013 |
| CHEN KUAN-YU | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 33 | 1999–2018 |
| Rochester, Minnesota, US | 1 | 1996 |