Inventor
Hanming Wu
Inventor
Shanghai, CN
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H01LSemiconductor devices19%
H01JElectric discharge tubes or discharge lamps6%
Y02PClimate change mitigation technologies in the production or processing of goods6%
A47JKitchen equipment3%
G06FElectric digital data processing3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
10,552,407Computing device for data managing and decision making202010,515,892TSV interconnect structure and manufacturing method thereof201910,128,117Semiconductor device, related manufacturing method, and related electronic device20189,799,525'Semiconductor device, related manufacturing method, and related electronic device'20179,648,985'Grill device'20179,590,031'Fin-type field effect transistor and manufacturing method thereof'20179,349,588'Method for fabricating quasi-SOI source/drain field effect transistor device'20169,024,281'Method for dual energy implantation for ultra-shallow junction formation of MOS devices'20158,901,675'CMOS devices and fabrication method'20148,551,831'Silicon germanium and polysilicon gate structure for strained silicon transistors'20138,466,050'Method for dual energy implantation for ultra-shallow junction formation of MOS devices'20138,106,423'Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors'20127,709,336'Metal hard mask method and structure for strained silicon MOS transistors'20107,591,659'Method and structure for second spacer formation for strained silicon MOS transistors'20097,557,000'Etching method and structure using a hard mask for strained silicon MOS transistors'20097,425,488'Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2015Patents assigned to SEMICONDUCTOR MFG INT SHANGHAI (8)· patent assignee history
2008–2018Based in Shanghai, CN· patent location history
2012–2013Patents assigned to CHEN JOHN (3)· patent assignee history
2012–2013Patents assigned to WU HANMING (3)· patent assignee history
2013Patents assigned to BONFANTI PAOLO (1)· patent assignee history
2016–2019Based in Beijing, CN· patent location history
2017–2019Patents assigned to SEMICONDUCTOR MFG INT SHANGHAI CORP (4)· patent assignee history
2017Based in Fujian, CN· patent location history
2020Based in Taipei, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SEMICONDUCTOR MFG INT SHANGHAI | 8 | 2008–2015 |
| SEMICONDUCTOR MFG INT SHANGHAI CORP | 4 | 2017–2019 |
| CHEN JOHN | 3 | 2012–2013 |
| WU HANMINGself | 3 | 2012–2013 |
| BONFANTI PAOLO | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Shanghai, CN | 12 | 2008–2018 |
| Beijing, CN | 2 | 2016–2019 |
| Taipei, TW | 1 | 2020 |
| Fujian, CN | 1 | 2017 |