Inventor
Soroush Abbaspour
Inventor
Fishkill, NY, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing94%
H03MCoding6%
PatentTitleYear
8,549,452'Method for supporting multiple libraries characterized at different process, voltage and temperature points'20138,515,725'Characterization of nonlinear cell macro model for timing analysis'20138,463,571'Performing reliability analysis of signal wires'20138,396,910'Efficient compression and handling of model library waveforms'20138,359,563'Moment-based characterization waveform for static timing analysis'20138,239,810'Method and system for optimizing a device with current source models'20128,122,411'Method of performing static timing analysis considering abstracted cell\'s interconnect parasitics'20128,108,815'Order independent method of performing statistical N-way maximum/minimum operation for non-Gaussian and non-linear distributions'20128,103,997'Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits'20128,020,129'Multiple voltage threshold timing analysis for a digital integrated circuit'20117,941,775'Arbitrary waveform propagation through a logic gate using timing analysis results'20117,814,448'Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits'20107,788,617'Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis'20107,739,640'Method and apparatus for static timing analysis in the presence of a coupling event and process variation'20107,685,549'Method of constrained aggressor set selection for crosstalk induced noise'20107,594,209'Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis'20097,552,412'Integrated circuit (IC) chip design method, program product and system'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2013Patents assigned to IBM (17)· patent assignee history
2009–2011Based in Fishkill, NY, US· patent location history
2012–2013Patents assigned to ABBASPOUR SOROUSH (9)· patent assignee history
2012–2013Patents assigned to FELDMANN PETER (7)· patent assignee history
2012–2013Patents assigned to HATAMI SAFAR (2)· patent assignee history
2012Patents assigned to SINHA DEBJIT (2)· patent assignee history
2012–2013Based in Ossining, NY, US· patent location history
2012Based in Hopewell Jct., NY, US· patent location history
2013Based in Hopewell Junction, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 17 | 2009–2013 |
| ABBASPOUR SOROUSHself | 9 | 2012–2013 |
| FELDMANN PETER | 7 | 2012–2013 |
| HATAMI SAFAR | 2 | 2012–2013 |
| SINHA DEBJIT | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fishkill, New York, US | 8 | 2009–2011 |
| Ossining, New York, US | 6 | 2012–2013 |
| Hopewell Jct., New York, US | 2 | 2012 |
| Hopewell Junction, New York, US | 1 | 2013 |