Inventor
Peter A. Habitz
Inventor
Hinesburg, VT, US
Overview
Patents· 82 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing64%
G01RMeasuring electric variables16%
H10DInorganic electric semiconductor devices5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y02PClimate change mitigation technologies in the production or processing of goods3%
G05BControl or regulating systems in general2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,489,540Integrating manufacturing feedback into integrated circuit structure design20199,858,368'Integrating manufacturing feedback into integrated circuit structure design'20189,378,328'Modeling multi-patterning variability with statistical timing'20169,323,875'Dynamically determining number of simulations required for characterizing intra-circuit incongruent variations'20169,171,124'Parasitic extraction in an integrated circuit with multi-patterning requirements'20159,157,956'Adaptive power control using timing canonicals'20159,104,834'Systems and methods for single cell product path delay analysis'20159,058,034'Integrated circuit product yield optimization using the results of performance path testing'20158,949,765'Modeling multi-patterning variability with statistical timing'20158,904,329'Systems and methods for single cell product path delay analysis'20148,856,709'Systems and methods for correlated parameters in statistical static timing analysis'20148,855,993'Integrated circuit design simulation matrix interpolation'20148,850,378'Hierarchical design of integrated circuits with multi-patterning requirements'20148,832,625'Systems and methods for correlated parameters in statistical static timing analysis'20148,806,402'Modeling multi-patterning variability with statistical timing'20148,769,452'Parasitic extraction in an integrated circuit with multi-patterning requirements'20148,768,679'System and method for efficient modeling of NPskew effects on static timing tests'20148,726,201'Method and system to predict a number of electromigration critical elements'20148,707,233'Systems and methods for correlated parameters in statistical static timing analysis'20148,656,207'Method for modeling variation in a feedback loop of a phase-locked loop'20148,571,825'Design-dependent integrated circuit disposition'20138,560,989'Statistical clock cycle computation'20138,543,966'Test path selection and test program generation for performance testing integrated circuit chips'20138,538,715'Design-dependent integrated circuit disposition'20138,539,429'System yield optimization using the results of integrated circuit chip performance path testing'20138,490,040'Disposition of integrated circuits using performance sort ring oscillator and performance path testing'20138,468,483'Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence'20138,458,632'Efficient slack projection for truncated distributions'20138,448,110'Method to reduce delay variation by sensitivity cancellation'20138,413,095'Statistical single library including on chip variation for rapid timing and power analysis'20138,239,810'Method and system for optimizing a device with current source models'20128,217,671'Parallel array architecture for constant current electro-migration stress testing'20128,141,012'Timing closure on multiple selective corners in a single statistical timing run'20128,141,025'Method of performing timing analysis on integrated circuit chips with consideration of process variations'20128,141,014'System and method for common history pessimism relief during static timing analysis'20128,108,816'Device history based delay variation adjustment during static timing analysis'20128,086,988'Chip design and fabrication method optimized for profit'20118,056,035'Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing'20117,962,874'Method and system for evaluating timing in an integrated circuit'20117,961,932'Method and apparatus for manufacturing diamond shaped chips'20117,886,246'Methods for identifying failing timing requirements in a digital design'20117,870,525'Slack sensitivity to parameter variation based timing analysis'20117,865,861'Method of generating wiring routes with matching delay in the presence of process variation'20117,856,607'System and method for generating at-speed structural tests to improve process and environmental parameter space coverage'20107,844,932'Method to identify timing violations outside of manufacturing specification limits'20107,823,115'Method of generating wiring routes with matching delay in the presence of process variation'20107,797,657'Parameter ordering for multi-corner static timing analysis'20107,784,003'Estimation of process variation impact of slack in multi-corner path-based static timing analysis'20107,750,648'Method to quickly estimate inductance for timing models'20107,716,616'Slack sensitivity to parameter variation based timing analysis'20107,684,969'Forming statistical model of independently variable parameters for timing analysis'20107,681,157'Variable threshold system and method for multi-corner static timing analysis'20107,669,159'IC tiling pattern method, IC so formed and analysis method'20107,620,921'IC chip at-functional-speed testing with process coverage evaluation'20097,555,740'Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis'20097,489,204'Method and structure for chip-level testing of wire delay independent of silicon delay'20097,464,359'Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure'20087,444,608'Method and system for evaluating timing in an integrated circuit'20087,418,689'Method of generating wiring routes with matching delay in the presence of process variation'20087,401,307'Slack sensitivity to parameter variation based timing analysis'20087,302,673'Method and system for performing shapes correction of a multi-cell reticle photomask design'20077,289,659'Method and apparatus for manufacturing diamond shaped chips'20077,266,474'Ring oscillator structure and method of separating random and systematic tolerance values'20077,181,711'Prioritizing of nets for coupled noise analysis'20077,089,129'Electromigration check of signal nets using net capacitance to evaluate thermal characteristics'20067,089,143'Method and system for evaluating timing in an integrated circuit'20066,948,146'Simplified tiling pattern method'20056,854,099'Balanced accuracy for extraction'20056,848,089'Method and apparatus for detecting devices that can latchup'20056,757,876'Method for use of hierarchy in extraction'20046,624,651'Kerf circuit for modeling of BEOL capacitances'20036,574,782'Decoupled capacitance calculator for orthogonal wiring patterns'20036,519,752'Method of performing parasitic extraction for a multi-fingered transistor'20036,490,708'Method of integrated circuit design by selection of noise tolerant gates'20026,477,686'Method of calculating 3-dimensional fringe characteristics using specially formed extension shapes'20026,473,887'Inclusion of global wires in capacitance extraction'20026,460,167'Efficient system for multi-level shape interactions'20026,430,729'Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing'20026,185,722'Three dimensional track-based parasitic extraction'20015,761,080'Method and apparatus for modeling capacitance in an integrated circuit'19985,045,911'Lateral PNP transistor and method for forming same'19914,996,164'Method for forming lateral PNP transistor'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2019Patents assigned to IBM (80)· patent assignee history
1991Based in Wappingers Falls, NY, US· patent location history
1998–2019Based in Hinesburg, VT, US· patent location history
2010Based in Hinesberg, VT, US· patent location history
2011–2018Patents assigned to HABITZ PETER A (24)· patent assignee history
2011–2018Patents assigned to FOREMAN ERIC A (15)· patent assignee history
2011–2018Patents assigned to VISWESWARIAH CHANDRAMOULI (9)· patent assignee history
2012–2018Patents assigned to HEMMETT JEFFREY G (11)· patent assignee history
2012Based in Essex Junction, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 80 | 1991–2019 |
| HABITZ PETER Aself | 24 | 2011–2018 |
| FOREMAN ERIC A | 15 | 2011–2018 |
| HEMMETT JEFFREY G | 11 | 2012–2018 |
| VISWESWARIAH CHANDRAMOULI | 9 | 2011–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hinesburg, VT, US | 76 | 1998–2019 |
| Essex Junction, VT, US | 3 | 2012 |
| Wappingers Falls, New York, US | 2 | 1991 |
| Hinesberg, VT, US | 1 | 2010 |