Inventor
Weng Chang
Inventor
Hsinchu, TW
Overview
Patents· 53 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
H10DInorganic electric semiconductor devices20%
H01LSemiconductor devices16%
C23CCoating metallic material3%
B24BMachines, devices, or processes for grinding or polishing2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry1%
B82YSpecific uses or applications of nanostructures1%
C01BNon-metallic elements1%
PatentTitleYear
10,879,370Etching back and selective deposition of metal gate202010,867,869Method for patterning a lanthanum containing layer202010,868,013Semiconductor device and method202010,861,751Method of semiconductor integrated circuit fabrication202010,699,966Semiconductor device with profiled work-function metal gate electrode and method of making202010,510,854Semiconductor device having gate body and inhibitor film between conductive prelayer over gate body and conductive layer over inhibitor film201910,510,756Semiconductor device and method201910,510,621Methods for threshold voltage tuning and structures formed thereby201910,504,795Method for patterning a lanthanum containing layer201910,483,170Method of semiconductor integrated circuit fabrication201910,304,835Semiconductor device and method201910,297,453Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby201910,014,382Semiconductor device with sidewall passivation and method of making201810,008,418Method of semiconductor integrated circuit fabrication20189,978,601Methods for pre-deposition treatment of a work-function metal layer20189,947,540Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby20189,761,683'Semiconductor device and manufacturing method thereof'20179,590,065'Semiconductor device with metal gate structure comprising work-function metal layer and work-fuction adjustment layer'20179,293,334'N metal for FinFET and methods of forming'20169,064,857'N metal for FinFET'20158,846,461'Silicon layer for stopping dislocation propagation'20148,344,447'Silicon layer for stopping dislocation propagation'20138,258,588'Sealing layer of a field effect transistor'20127,834,389'Triangular space element for semiconductor device'20107,375,040'Etch stop layer'20087,253,524'Copper interconnects'20077,193,325'Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects'20077,119,404'High performance strained channel MOSFETs by coupled stress effects'20067,114,450'Magazine for receiving electric shock bullets'20067,115,974'Silicon oxycarbide and silicon carbonitride based materials for MOS devices'20067,002,177'Test region layout for shallow trench isolation'20066,929,533'Methods for enhancing within-wafer CMP uniformity'20056,828,245'Method of improving an etching profile in dual damascene etching'20046,767,274'Method to reduce defect/slurry residue for copper CMP'20046,753,249'Multilayer interface in copper CMP for low K dielectric'20046,576,551'Chemical mechanical polish planarizing method with pressure compensating layer'20036,518,183'Hillock inhibiting method for forming a passivated copper containing conductor layer'20036,472,312'Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation'20026,403,464'Method to reduce the moisture content in an organic low dielectric constant material'20026,383,935'Method of reducing dishing and erosion using a sacrificial layer'20026,376,377'Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity'20026,372,632'Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer'20026,350,694'Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials'20026,346,476'Method for enhancing line-to-line capacitance uniformity of plasma enhanced chemical vapor deposited (PECVD) inter-metal dielectric (IMD) layers'20026,319,809'Method to reduce via poison in low-k Cu dual damascene by UV-treatment'20016,274,483'Method to improve metal line adhesion by trench corner shape modification'20016,271,138'Chemical mechanical polish (CMP) planarizing method with enhanced chemical mechanical polish (CMP) planarized layer planarity'20016,268,294'Method of protecting a low-K dielectric material'20016,255,232'Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer'20016,187,663'Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials'20016,159,842'Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections'20006,043,152'Method to reduce metal damage in the HDP-CVD process by using a sacrificial dielectric film'20005,514,350'Apparatus for making nanostructured ceramic powders and whiskers'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996Based in Somerset, NJ, US· patent location history
2000–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (31)· patent assignee history
2000–2008Based in Taipei, TW· patent location history
2001–2006Patents assigned to TAIWAN SEMICONDUCTOR MANFACTUR (2)· patent assignee history
2005–2020Based in Hsinchu, TW· patent location history
2006Patents assigned to CHANG WENG-PING (1)· patent assignee history
2006Based in Pingtung County, TW· patent location history
2012–2013Patents assigned to CHANG WENG (2)· patent assignee history
2017–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (18)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 31 | 2000–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 18 | 2017–2020 |
| CHANG WENGself | 2 | 2012–2013 |
| TAIWAN SEMICONDUCTOR MANFACTUR | 2 | 2001–2006 |
| CHANG WENG-PINGself | 1 | 2006 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 28 | 2005–2020 |
| Taipei, TW | 23 | 2000–2008 |
| Pingtung County, TW | 1 | 2006 |
| Somerset, New Jersey, US | 1 | 1996 |