Inventor
SRINIVAS PIETAMBARAM
Inventor
US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H01FMagnets9%
H10DInorganic electric semiconductor devices4%
H05KPrinted circuits3%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%
H01GCapacitors2%
G02BOptical elements, systems or apparatus1%
H01PWaveguides1%
PatentTitleYear
12,568,831Patternable die attach materials and processes for patterning202612,449,600Position controlled waveguides and methods of manufacturing the same202512,444,672Hybrid bonding technologies with thermal expansion compensation structures202512,394,719Methods and apparatus to increase glass core thickness202512,374,482Carrier chuck comprising a plurality of magnets and methods of forming and using thereof202512,354,931Optimization for raster scanning202512,334,422Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates202512,336,197In-plane inductors in IC packages202512,308,329Chiplet first architecture for die tiling applications202512,272,484Coreless electronic substrates having embedded inductors202512,272,656Heterogeneous nested interposer package for IC chips202512,255,147Electronic substrate having an embedded etch stop to control cavity depth in glass layers therein202512,243,825Hybrid conductive vias for electronic substrates202512,230,430Substrate embedded magnetic core inductors and method of making202512,224,103Angled inductor with small form factor202512,199,048Heterogeneous nested interposer package for IC chips202512,191,240Hybrid glass core for wafer level and panel level packaging applications202512,165,994Radio frequency antennas and waveguides for communication between integrated circuit devices202412,125,793Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications202412,087,695Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications202411,990,427Chiplet first architecture for die tiling applications202411,978,685Glass core patch with in situ fabricated fan-out layer to enable die tiling applications202411,973,041Chiplet first architecture for die tiling applications202411,935,857Surface finishes with low RBTV for fine and mixed bump pitch architectures202411,929,212Method to form high capacitance thin film capacitors (TFCs) as embedded passives in organic substrate packages202411,923,312Patternable die attach materials and processes for patterning202411,862,619Patch accommodating embedded dies having different thicknesses202411,855,125Capacitors with nanoislands on conductive plates202311,824,018Heterogeneous nested interposer package for IC chips202311,817,349Conductive route patterning for electronic substrates202311,780,210Glass dielectric layer with patterning202311,769,735Chiplet first architecture for die tiling applications202311,756,890Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications202311,735,533Heterogeneous nested interposer package for IC chips202311,728,265Selective deposition of embedded thin-film resistors for semiconductor packaging202311,622,448Sandwich-molded cores for high-inductance architectures202311,574,993Package architecture with tunable magnetic properties for embedded devices202311,488,918Surface finishes with low rBTV for fine and mixed bump pitch architectures202211,443,885Thin film barrier seed metallization in magnetic-plugged through hole inductor202211,355,438Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications202211,348,718Substrate embedded magnetic core inductors and method of making202211,322,290Techniques for an inductor at a first level interface202211,309,239Electromigration resistant and profile consistent contact arrays202211,270,959Enabling magnetic films in inductors integrated into semiconductor packages202211,264,307Dual-damascene zero-misalignment-via process for semiconductor packaging2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to INTEL CORP (45)· patent assignee history
2022–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 45 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 45 | 2022–2026 |