Inventor

Teruhito Ohnishi

Inventor
Osaka, JP

Overview

32→
Patents
1993–2010
Patent span
Electricity
Primary field (CPC H)

Patents· 32 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices42%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
C30BSingle-crystal growth4%
H10BElectronic memory devices4%
G01KMeasuring temperature2%
H01FMagnets2%
H05KPrinted circuits2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
7,808,358'Inductor and method for fabricating the same'20107,719,031'Heterojunction biploar transistor and method for manufacturing same'20107,465,969'Bipolar transistor and method for fabricating the same'20087,145,168'Semiconductor device'20067,135,721'Heterojunction bipolar transistor having reduced driving voltage requirements'20067,129,168'Method of estimating substrate temperature'20067,109,095'Method for fabricating semiconductor device'20067,091,099'Bipolar transistor and method for fabricating the same'20067,049,681'Bipolar transistor device having phosphorous'20066,987,072'Method of producing semiconductor crystal'20066,939,772'Bipolar transistor and fabrication method thereof'20056,927,118'Method of fabricating a bipolar transistor utilizing a dry etching and a wet etching to define a base junction opening'20056,917,075'Semiconductor device'20056,867,107'Variable capacitance device and process for manufacturing the same'20056,861,316'Semiconductor device and method for fabricating the same'20056,847,063'Semiconductor device'20056,847,062'Semiconductor device'20056,838,395'Method for fabricating a semiconductor crystal'20056,828,602'Bipolar transistor and method manufacture thereof'20046,800,532'Method of manufacturing a semiconductor device comprising a bipolar transistor and a variable capacitor'20046,759,697'Heterojunction bipolar transistor'20046,674,149'Bipolar transistor device having phosphorous'20046,642,607'Semiconductor device'20036,620,665'Method for fabricating semiconductor device'20036,399,993'Semiconductor device and method for fabricating the same'20026,214,126'Method for cleaning a silicon substrate'20015,500,379'Method of manufacturing semiconductor device'19965,472,826'Semiconductor device fabrication method'19955,449,934'Semiconductor memory device and process'19955,365,095'Semiconductor memory device and process'19945,327,012'Semiconductor device having a double-layer interconnection structure'19945,198,884'Semiconductor devices having a double-layer interconnection structure'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2006Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (29)· patent assignee history
1993–2010Based in Osaka, JP· patent location history
2001–2010Based in Hirakata, JP· patent location history
2008–2010Patents assigned to PANASONIC CORP (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MATSUSHITA ELECTRIC INDUSTRIAL CO LTD291993–2006
PANASONIC CORP32008–2010
Locations
LocationPatentsSpan
Osaka, JP221993–2010
Hirakata, JP102001–2010