Inventor

Parag R. Maharana

Inventor
Fremont, CA, US

Overview

23→
Patents
2005–2021
Patent span
Physics
Primary field (CPC G)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing66%
G06NComputing arrangements based on specific computational models16%
H04LTransmission of digital information, e.g. telegraphic communication16%
G11CStatic stores3%
PatentTitleYear
11,099,789Remote direct memory access in multi-tier memory systems202111,068,203NVMe direct virtualization with configurable storage202110,880,401Optimization of data access and communication in memory systems202010,877,892Predictive paging to accelerate memory access202010,691,611Isolated performance domains in a memory system202010,671,460Memory access communications through message passing interface implemented in memory systems20209,977,626Implementing scattered atomic I/O writes20189,400,759'Cache load balancing in storage controllers'20169,378,152'Systems and methods for I/O processing using out-of-band hinting to block driver or storage controller'20169,239,679'System for efficient caching of swap I/O and/or similar I/O pattern(s)'20169,201,681'Method and controller device for quality of service (QOS) caching in a virtualized environment'20159,189,409'Reducing writes to solid state drive cache memories of storage controllers'20159,135,044'Virtual function boot in multi-root I/O virtualization environments to enable multiple servers to share virtual functions of a storage adapter through a MR-IOV switch'20159,110,813'Cache load balancing in storage controllers'20158,984,234'Subtractive validation of cache lines for virtual machines'20158,954,788'Methods and structure for single root input/output virtualization enhancement in peripheral component interconnect express systems'20157,917,659'Variable length command pull with contiguous sequential layout'20117,836,351'System for providing an alternative communication path in a SAS cluster'20107,788,420'Address buffer mode switching for varying request sizes'20107,552,355'System for providing an alternative communication path in a SAS cluster'20097,082,498'Online RAID migration without non-volatile memory'20067,024,585'Method, apparatus, and program for data mirroring with striped hotspare'20066,928,514'Method and apparatus for teaming storage controllers'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2009Patents assigned to LSI LOGIC CORP (4)· patent assignee history
2005–2016Based in Fremont, CA, US· patent location history
2010–2016Patents assigned to LSI CORP (10)· patent assignee history
2015–2016Patents assigned to AVAGO TECHNOLOGIES GENERAL IP (7)· patent assignee history
2015Patents assigned to MAHARANA PARAG R (1)· patent assignee history
2018–2021Based in Dublin, CA, US· patent location history
2020–2021Patents assigned to MICRON TECHNOLOGY INC (6)· patent assignee history
2021Based in Dublin, OH, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LSI CORP102010–2016
AVAGO TECHNOLOGIES GENERAL IP72015–2016
MICRON TECHNOLOGY INC62020–2021
LSI LOGIC CORP42005–2009
MAHARANA PARAG Rself12015
Locations
LocationPatentsSpan
Fremont, California, US162005–2016
Dublin, California, US62018–2021
Dublin, OH, US12021