Inventor
Gad Sheaffer
Inventor
Haifa, IL
Overview
Patents· 92 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing79%
G06TImage data processing or generation, in general5%
H04LTransmission of digital information, e.g. telegraphic communication3%
G02BOptical elements, systems or apparatus2%
G09GArrangements or circuits for control of indicating devices using static means to present variable information2%
H04NPictorial communication, e.g. television2%
B60QArrangement of signalling or lighting devices, the mounting or supporting thereof or circuits therefor, for vehicles in general1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
G06KGraphical data reading1%
PatentTitleYear
10,976,269Wafer alignment for small-angle x-ray scatterometry202110,229,523Augmented reality alteration detector20199,836,650Identification of a photographer based on an image20179,785,462'Registering a user-handler in hardware for transactional memory event handling'20179,767,027'Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy'20179,747,221'Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform'20179,658,880'Efficient garbage collection and exception handling in a hardware accelerated transactional memory system'20179,626,773'Augmented reality alteration detector'20179,619,298'Scheduling computing tasks for multi-processor systems based on resource requirements'20179,588,771'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20179,524,240'Obscuring memory access patterns in conjunction with deadlock detection or avoidance'20169,477,515'Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode'20169,471,129'Determining a write operation'20169,459,874'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20169,430,350'Instance monitor'20169,350,909'Remotely controlled crowd-sourced media capture'20169,280,397'Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata'20169,195,600'Mechanisms to accelerate transactions using buffered stores'20159,164,923'Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform'20159,100,938'Digital relay for out of network devices'20159,092,253'Instrumentation of hardware assisted transactional memory system'20159,069,670'Mechanisms to accelerate transactions using buffered stores'20159,003,421'Acceleration threads on idle OS-visible thread execution units'20158,914,618'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20148,886,894'Mechanisms to accelerate transactions using buffered stores'20148,856,466'Mechanisms to accelerate transactions using buffered stores'20148,838,908'Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM'20148,812,796'Private memory regions and coherence optimizations'20148,812,792'Technique for using memory attributes'20148,806,101'Metaphysical address space for holding lossy metadata in hardware'20148,799,582'Extending cache coherency protocols to support locally buffered data'20148,769,212'Memory model for hardware attributes within a transactional memory system'20148,719,514'Software filtering in a transactional memory system'20148,688,951'Operating system virtual memory management for hardware transactional memory'20148,688,917'Read and write monitoring attributes in transactional memory (TM) systems'20148,627,017'Read and write monitoring attributes in transactional memory (TM) systems'20148,627,014'Memory model for hardware attributes within a transactional memory system'20148,560,781'Technique for using memory attributes'20138,539,465'Accelerating unbounded memory transactions using nested cache resident transactions'20138,521,995'Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode'20138,516,201'Protecting private data from cache attacks'20138,489,864'Performing escape actions in transactions'20138,473,921'Debugging mechanisms in a cache-based memory isolation system'20138,407,425'Obscuring memory access patterns in conjunction with deadlock detection or avoidance'20138,402,218'Efficient garbage collection and exception handling in a hardware accelerated transactional memory system'20138,392,929'Leveraging memory isolation hardware technology to efficiently detect race conditions'20138,370,577'Metaphysically addressed cache metadata'20138,365,016'Performing mode switching in an unbounded transactional memory (UTM) system'20138,359,433'Method and system of handling non-aligned memory accesses'20138,356,166'Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers'20138,341,356'Protected cache architecture and secure programming paradigm to protect applications'20128,316,194'Mechanisms to accelerate transactions using buffered stores'20128,250,331'Operating system virtual memory management for hardware transactional memory'20128,209,689'Live lock free priority scheme for memory transactions in transactional memory'20128,161,247'Wait loss synchronization'20128,140,773'Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM'20128,095,824'Performing mode switching in an unbounded transactional memory (UTM) system'20127,991,965'Technique for using memory attributes'20117,975,129'Selective hardware lock disabling'20117,958,320'Protected cache architecture and secure programming paradigm to protect applications'20117,613,908'Selective hardware lock disabling'20097,587,584'Mechanism to exploit synchronization overhead to improve multithreaded performance'20097,454,601'N-wide add-compare-select instruction'20087,437,581'Method and apparatus for varying energy per instruction according to the amount of available parallelism'20087,293,056'Variable width, at least six-way addition/accumulation instructions'20077,260,592'Addressing mode and/or instruction for providing sine and cosine value pairs'20077,257,728'Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs'20077,028,171'Multi-way select instructions using accumulated condition codes'20067,007,187'Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs'20066,976,049'Method and apparatus for implementing single/dual packed multi-way addition instructions having accumulation options'20056,965,962'Method and system to overlap pointer load cache misses'20056,957,321'Instruction set extension using operand bearing NOP instructions'20056,944,750'Pre-steering register renamed instructions to execution unit associated locations in instruction cache'20056,928,605'Add-compare-select accelerator using pre-compare-select-add operation'20056,859,851'Buffer pre-loading for memory service interruptions'20056,779,104'Method and apparatus for pre-processing instructions for a processor'20046,732,257'Reducing the length of lower level instructions by splitting and recombining an immediate'20046,715,064'Method and apparatus for performing sequential executions of elements in cooperation with a transform'20046,594,754'Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters'20036,593,930'Method and apparatus to execute a memory maintenance operation during a screen blanking interval'20036,539,471'Method and apparatus for pre-processing instructions for a processor'20036,515,672'Managing prefetching from a data buffer'20036,470,444'Method and apparatus for dividing a store operation into pre-fetch and store micro-operations'20026,351,802'Method and apparatus for constructing a pre-scheduled instruction cache'20026,105,124'Method and apparatus for merging binary translated basic blocks of instructions'20006,055,630'System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units'20005,909,573'Method of branch prediction using loop counters'19995,838,941'Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers'19985,818,745'Computer for performing non-restoring division'19985,790,822'Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor'19985,784,307'Division algorithm for floating point or integer numbers'19985,710,902'Instruction dependency chain indentifier'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2017Patents assigned to INTEL CORP (68)· patent assignee history
1998–2021Based in Haifa, IL· patent location history
2000–2002Based in Beaverton, OR, US· patent location history
2012–2017Patents assigned to SHEAFFER GAD (36)· patent assignee history
2012–2016Patents assigned to ADL-TABATABAI ALI-REZA (20)· patent assignee history
2012–2016Patents assigned to GRAY JAN (17)· patent assignee history
2012–2017Patents assigned to BASSIN VADIM (15)· patent assignee history
2014Based in Hafia, IL· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 68 | 1998–2017 |
| SHEAFFER GADself | 36 | 2012–2017 |
| ADL-TABATABAI ALI-REZA | 20 | 2012–2016 |
| GRAY JAN | 17 | 2012–2016 |
| BASSIN VADIM | 15 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Haifa, IL | 89 | 1998–2021 |
| Beaverton, OR, US | 2 | 2000–2002 |
| Hafia, IL | 1 | 2014 |