Inventor

Julien Frougier

Inventor

Albany, NY, US

Overview

2018–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 80 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices27%

H10DInorganic electric semiconductor devices27%

B82YSpecific uses or applications of nanostructures12%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

H10BElectronic memory devices6%

H10NElectric solid-state devices not otherwise provided for3%

H04LTransmission of digital information, e.g. telegraphic communication1%

G06NComputing arrangements based on specific computational models0%

G11CStatic stores0%

PatentTitleYear

11,121,087Methods of forming a conductive contact structure to an embedded memory device on an IC product and a corresponding IC product2021 11,121,233Forming nanosheet transistor using sacrificial spacer and inner spacers2021 11,107,827Integration of split gate metal-oxide-nitride-oxide-semiconductor memory with vertical FET2021 11,101,348Nanosheet field effect transistor with spacers between sheets2021 11,094,794Air spacer structures2021 11,094,803Nanosheet device with tall suspension and tight contacted gate poly-pitch2021 11,094,784Gate-all-around field effect transistor having stacked U shaped channels configured to improve the effective width of the transistor2021 11,069,819Field-effect transistors with channel regions that include a two-dimensional material on a mandrel2021 11,069,744Steep-switch vertical field effect transistor2021 11,049,934Transistor comprising a matrix of nanowires and methods of making such a transistor2021 11,043,411Integration of air spacer with self-aligned contact in transistor2021 11,011,638Transistor having airgap spacer around gate structure2021 10,991,808Steep-switch field effect transistor with integrated bi-stable resistive system2021 10,964,750Steep-switch field effect transistor with integrated bi-stable resistive system2021 10,957,799Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions2021 10,950,610Asymmetric gate cut isolation for SRAM2021 10,923,590Wrap-around contact for vertical field effect transistors2021 10,909,443Neuromorphic circuit structure and method to form same2021 10,903,369Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions2021 10,903,317Gate-all-around field effect transistors with robust inner spacers and methods2021 10,903,331Positioning air-gap spacers in a transistor for improved control of parasitic capacitance2021 10,903,315Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection2021 10,886,378Method of forming air-gap spacers and gate contact over active region and the resulting device2021 10,872,962Steep-switch field effect transistor with integrated bi-stable resistive system2020 10,840,146Structures and SRAM bit cells with a buried cross-couple interconnect2020 10,832,954Forming a reliable wrap-around contact without source/drain sacrificial regions2020 10,833,191Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate2020 10,818,803Fin-type field-effect transistors including a two-dimensional material2020 10,818,792Nanosheet field-effect transistors formed with sacrificial spacers2020 10,818,674Structures and SRAM bit cells integrating complementary field-effect transistors2020 10,804,398Method of forming wrap-around-contact and the resulting device2020 10,790,376Contact structures2020 10,784,171Vertically stacked complementary-FET device with independent gate control2020 10,770,566Unique gate cap and gate cap spacer structures for devices on integrated circuit products2020 10,756,203Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism2020 10,741,675Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism2020 10,741,639Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection2020 10,734,525Gate-all-around transistor with spacer support and methods of forming same2020 10,714,567Nanosheet field-effect transistor with substrate isolation2020 10,692,991Gate-all-around field effect transistors with air-gap inner spacers and methods2020 10,679,894Airgap spacers formed in conjunction with a late gate cut2020 10,665,669Insulative structure with diffusion break integral with isolation layer and methods to form same2020 10,665,692Non-self aligned gate contacts formed over the active region of a transistor2020 10,651,291Inner spacer formation in a nanosheet field-effect transistor2020 10,644,157Fin-type field effect transistors with uniform channel lengths and below-channel isolation on bulk semiconductor substrates and methods2020 10,629,516Hybrid dual damascene structures with enlarged contacts2020 10,608,082Field-effect transistors including multiple gate lengths2020 10,586,856Nanosheet FET device with epitaxial nucleation2020 10,580,692Integration of air spacer with self-aligned contact in transistor2020 10,573,755Nanosheet FET with box isolation on substrate2020 10,566,436Steep-switch field effect transistor with integrated bi-stable resistive system2020 10,559,656Wrap-all-around contact for nanosheet-FET and method of forming same2020 10,553,705Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism2020 10,546,945Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism2020 10,541,272Steep-switch vertical field effect transistor2020 10,529,826Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices2020 10,510,620Work function metal patterning for N-P space between active nanostructures2019 10,510,622Vertically stacked complementary-FET device with independent gate control2019 10,475,899Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby2019 10,431,663Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure2019 10,424,651Forming nanosheet transistor using sacrificial spacer and inner spacers2019 10,418,484Vertical field effect transistors incorporating U-shaped semiconductor bodies and methods2019 10,388,760Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism2019 10,388,732Nanosheet field-effect transistors including a two-dimensional semiconducting material2019 10,381,459Transistors with H-shaped or U-shaped channels and method for forming the same2019 10,332,803Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming2019 10,290,549Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same2019 10,276,442Wrap-around contacts formed with multiple silicide layers2019 10,269,983Stacked nanosheet field-effect transistor with air gap spacers2019 10,256,158Insulated epitaxial structures in nanosheet complementary field effect transistors2019 10,256,316Steep-switch field effect transistor with integrated bi-stable resistive system2019 10,236,292Complementary FETs with wrap around contacts and methods of forming same2019 10,236,218Methods, apparatus and system for forming wrap-around contact with dual silicide2019 10,236,379Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process2019 10,192,867Complementary FETs with wrap around contacts and method of forming same2019 10,170,520Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system2019 10,164,041Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby2018 10,014,390Inner spacer formation for nanosheet field-effect transistors with tall suspensions2018 9,991,352Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device2018 9,947,804Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure2018

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2018–2021Patents assigned to GLOBALFOUNDRIES INC (41)· patent assignee history

2018–2021Based in Albany, NY, US· patent location history

2019–2021Patents assigned to IBM (31)· patent assignee history

2019Patents assigned to GLOBALFOUNDARIES INC (1)· patent assignee history

2021Patents assigned to GLOBALFOUNDRIES US INC (7)· patent assignee history

2021Patents assigned to TESSERA INC (1)· patent assignee history

2021Based in New Albany, OH, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
GLOBALFOUNDRIES INC	41	2018–2021
IBM	31	2019–2021
GLOBALFOUNDRIES US INC	7	2021
GLOBALFOUNDARIES INC	1	2019
TESSERA INC	1	2021

Locations

Location	Patents	Span
Albany, New York, US	76	2018–2021
New Albany, OH, US	4	2021