Inventor
Simon John Molloy
Inventor
Allentown, PA, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices28%
H01LSemiconductor devices24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
B08BCleaning in general2%
PatentTitleYear
10,811,533Medium high voltage MOSFET device202010,741,684Integrated channel diode202010,672,901Power transistor with terminal trenches in terminal resurf regions202010,573,718Vertical high-voltage MOS transistor202010,553,717Medium voltage MOSFET device202010,541,326Multiple shielding trench gate FET202010,438,936Photo-sensitive silicon package embedding self-powered electronic system201910,256,337Power transistor with terminal trenches in terminal resurf regions201910,153,220Silicon package having electrical functionality by embedded passive components201810,121,716Silicon package for embedded semiconductor chip and power converter201810,109,614Silicon package for embedded electronic system having stacked semiconductor chips201810,062,624Silicon package for embedded semiconductor chip and power converter20189,905,638'Silicon epitaxy for high aspect ratio, substantially perpendicular deep silicon trench'20189,859,261'Photo-sensitive silicon package embedding self-powered electronic system'20189,818,662'Silicon package having electrical functionality by embedded passive components'20179,748,376'Power FET with integrated sensors and method of manufacturing'20179,721,860'Silicon package for embedded semiconductor chip and power converter'20179,711,639'Multiple shielding trench gate FET'20179,673,317'Integrated termination for multiple trench field plate'20179,640,519'Photo-sensitive silicon package embedding self-powered electronic system'20179,525,035'Vertical high-voltage MOS transistor and method of forming the same'20169,484,450'Integrated channel diode'20169,450,082'Integrated termination for multiple trench field plate'20169,356,133'Medium voltage MOSFET device'20169,305,852'Silicon package for embedded electronic system having stacked semiconductor chips'20169,299,830'Multiple shielding trench gate fet'20169,245,994'MOSFET with curved trench feature coupling termination trench to active trench'20169,230,851'Reduction of polysilicon residue in a trench for polysilicon trench filling processes'20169,136,381'Super junction MOSFET with integrated channel diode'20158,748,976'Dual RESURF trench field plate in vertical MOSFET'20148,294,210'High voltage channel diode'20128,288,820'High voltage power integrated circuit'20127,741,702'Semiconductor structure formed using a sacrificial structure'20107,339,274'Metallization performance in electronic devices'20087,329,605'Semiconductor structure formed using a sacrificial structure'20086,730,600'Method of dry etching a semiconductor device in the absence of a plasma'20046,656,850'Method for in-situ removal of side walls in MOM capacitor formation'20036,585,830'Method for cleaning tungsten from deposition wall chambers'20036,472,307'Methods for improved encapsulation of thick metal features in integrated circuit fabrication'20026,458,648'Method for in-situ removal of side walls in MOM capacitor formation'20026,406,999'Semiconductor device having reduced line width variations between tightly spaced and isolated features'20026,395,639'Process for improving line width variations between tightly spaced and isolated features in integrated circuits'20026,384,446'Grooved capacitor structure for integrated circuits'20026,265,235'Method of sectioning of photoresist for shape evaluation'20016,258,610'Method analyzing a semiconductor surface using line width metrology with auto-correlation operation'20016,218,085'Process for photoresist rework to avoid sodium incorporation'20016,180,518'Method for forming vias in a low dielectric constant material'20016,046,115'Method for removing etching residues and contaminants'20005,849,639'Method for removing etching residues and contaminants'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2001Patents assigned to LUCENT TECHNOLOGIES INC (5)· patent assignee history
1998–2003Based in Orlando, FL, US· patent location history
2001–2002Patents assigned to AGERE SYST GUARDIAN CORP (6)· patent assignee history
2003–2010Patents assigned to AGERE SYSTEMS INC (6)· patent assignee history
2003–2020Based in Allentown, PA, US· patent location history
2012–2020Patents assigned to TEXAS INSTRUMENTS INC (32)· patent assignee history
2012Patents assigned to KOCON CHRISTOPHER BOGUSLAW (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 32 | 2012–2020 |
| AGERE SYST GUARDIAN CORP | 6 | 2001–2002 |
| AGERE SYSTEMS INC | 6 | 2003–2010 |
| LUCENT TECHNOLOGIES INC | 5 | 1998–2001 |
| KOCON CHRISTOPHER BOGUSLAW | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Allentown, Pennsylvania, US | 37 | 2003–2020 |
| Orlando, Florida, US | 12 | 1998–2003 |